Commit ef9417e8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'iommu-updates-v4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu 

Pull IOMMU updates from Joerg Roedel:
 "This time there are not a lot of changes coming from the IOMMU side.

  That is partly because I returned from my parental leave late in the
  development process and probably partly because everyone was busy with
  Spectre and Meltdown mitigation work and didn't find the time for
  IOMMU work. So here are the few changes that queued up for this merge
  window:

   - 5-level page-table support for the Intel IOMMU.

   - error reporting improvements for the AMD IOMMU driver

   - additional DT bindings for ipmmu-vmsa (Renesas)

   - small fixes and cleanups"

* tag 'iommu-updates-v4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
  iommu: Clean up of_iommu_init_fn
  iommu/ipmmu-vmsa: Remove redundant of_iommu_init_fn hook
  iommu/msm: Claim bus ops on probe
  iommu/vt-d: Enable 5-level paging mode in the PASID entry
  iommu/vt-d: Add a check for 5-level paging support
  iommu/vt-d: Add a check for 1GB page support
  iommu/vt-d: Enable upto 57 bits of domain address width
  iommu/vt-d: Use domain instead of cache fetching
  iommu/exynos: Don't unconditionally steal bus ops
  iommu/omap: Fix debugfs_create_*() usage
  iommu/vt-d: clean up pr_irq if request_threaded_irq fails
  iommu: Check the result of iommu_group_get() for NULL
  iommu/ipmmu-vmsa: Add r8a779(70|95) DT bindings
  iommu/ipmmu-vmsa: Add r8a7796 DT binding
  iommu/amd: Set the device table entry PPR bit for IOMMU V2 devices
  iommu/amd - Record more information about unknown events
parents 605dc776 fedbd940

Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt

+3 −0
Original line number Original line Diff line number Diff line
@@ -16,6 +16,9 @@ Required Properties: 
    - "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.

    - "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.

    - "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU.

    - "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU.

    - "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU.

    - "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU.

    - "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.

    - "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU.

    - "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU.

    - "renesas,ipmmu-vmsa" for generic R-Car Gen2 VMSA-compatible IPMMU.

    - "renesas,ipmmu-vmsa" for generic R-Car Gen2 VMSA-compatible IPMMU.





  - reg: Base address and size of the IPMMU registers.

  - reg: Base address and size of the IPMMU registers.

drivers/iommu/amd_iommu.c

+18 −6
Original line number Original line Diff line number Diff line
@@ -617,7 +617,9 @@ retry: 
		       address, flags);

		       address, flags);

		break;

		break;

	default:

	default:

		printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);

		printk(KERN_ERR "UNKNOWN type=0x%02x event[0]=0x%08x "

		       "event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",

		       type, event[0], event[1], event[2], event[3]);

	}

	}





	memset(__evt, 0, 4 * sizeof(u32));

	memset(__evt, 0, 4 * sizeof(u32));
@@ -1816,7 +1818,8 @@ static bool dma_ops_domain(struct protection_domain *domain) 
	return domain->flags & PD_DMA_OPS_MASK;

	return domain->flags & PD_DMA_OPS_MASK;

}

}





static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)

static void set_dte_entry(u16 devid, struct protection_domain *domain,

			  bool ats, bool ppr)

{

{

	u64 pte_root = 0;

	u64 pte_root = 0;

	u64 flags = 0;

	u64 flags = 0;
@@ -1833,6 +1836,13 @@ static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) 
	if (ats)

	if (ats)

		flags |= DTE_FLAG_IOTLB;

		flags |= DTE_FLAG_IOTLB;





	if (ppr) {

		struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];



		if (iommu_feature(iommu, FEATURE_EPHSUP))

			pte_root |= 1ULL << DEV_ENTRY_PPR;

	}



	if (domain->flags & PD_IOMMUV2_MASK) {

	if (domain->flags & PD_IOMMUV2_MASK) {

		u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);

		u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);

		u64 glx  = domain->glx;

		u64 glx  = domain->glx;
@@ -1895,9 +1905,9 @@ static void do_attach(struct iommu_dev_data *dev_data, 
	domain->dev_cnt                 += 1;

	domain->dev_cnt                 += 1;





	/* Update device table */

	/* Update device table */

	set_dte_entry(dev_data->devid, domain, ats);

	set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);

	if (alias != dev_data->devid)

	if (alias != dev_data->devid)

		set_dte_entry(alias, domain, ats);

		set_dte_entry(alias, domain, ats, dev_data->iommu_v2);





	device_flush_dte(dev_data);

	device_flush_dte(dev_data);

}

}
@@ -2276,13 +2286,15 @@ static void update_device_table(struct protection_domain *domain) 
	struct iommu_dev_data *dev_data;

	struct iommu_dev_data *dev_data;





	list_for_each_entry(dev_data, &domain->dev_list, list) {

	list_for_each_entry(dev_data, &domain->dev_list, list) {

		set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);

		set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,

			      dev_data->iommu_v2);





		if (dev_data->devid == dev_data->alias)

		if (dev_data->devid == dev_data->alias)

			continue;

			continue;





		/* There is an alias, update device table entry for it */

		/* There is an alias, update device table entry for it */

		set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled);

		set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,

			      dev_data->iommu_v2);

	}

	}

}

}

drivers/iommu/amd_iommu_types.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -98,6 +98,7 @@ 
#define FEATURE_HE		(1ULL<<8)

#define FEATURE_HE		(1ULL<<8)

#define FEATURE_PC		(1ULL<<9)

#define FEATURE_PC		(1ULL<<9)

#define FEATURE_GAM_VAPIC	(1ULL<<21)

#define FEATURE_GAM_VAPIC	(1ULL<<21)

#define FEATURE_EPHSUP		(1ULL<<50)





#define FEATURE_PASID_SHIFT	32

#define FEATURE_PASID_SHIFT	32

#define FEATURE_PASID_MASK	(0x1fULL << FEATURE_PASID_SHIFT)

#define FEATURE_PASID_MASK	(0x1fULL << FEATURE_PASID_SHIFT)
@@ -192,6 +193,7 @@ 
/* macros and definitions for device table entries */

/* macros and definitions for device table entries */

#define DEV_ENTRY_VALID         0x00

#define DEV_ENTRY_VALID         0x00

#define DEV_ENTRY_TRANSLATION   0x01

#define DEV_ENTRY_TRANSLATION   0x01

#define DEV_ENTRY_PPR           0x34

#define DEV_ENTRY_IR            0x3d

#define DEV_ENTRY_IR            0x3d

#define DEV_ENTRY_IW            0x3e

#define DEV_ENTRY_IW            0x3e

#define DEV_ENTRY_NO_PAGE_FAULT	0x62

#define DEV_ENTRY_NO_PAGE_FAULT	0x62

drivers/iommu/arm-smmu-v3.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -2971,7 +2971,7 @@ static struct platform_driver arm_smmu_driver = { 
};

};

module_platform_driver(arm_smmu_driver);

module_platform_driver(arm_smmu_driver);





IOMMU_OF_DECLARE(arm_smmuv3, "arm,smmu-v3", NULL);

IOMMU_OF_DECLARE(arm_smmuv3, "arm,smmu-v3");





MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations");

MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations");

MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");

MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");

drivers/iommu/arm-smmu.c

+6 −6
Original line number Original line Diff line number Diff line
@@ -2211,12 +2211,12 @@ static struct platform_driver arm_smmu_driver = { 
};

};

module_platform_driver(arm_smmu_driver);

module_platform_driver(arm_smmu_driver);





IOMMU_OF_DECLARE(arm_smmuv1, "arm,smmu-v1", NULL);

IOMMU_OF_DECLARE(arm_smmuv1, "arm,smmu-v1");

IOMMU_OF_DECLARE(arm_smmuv2, "arm,smmu-v2", NULL);

IOMMU_OF_DECLARE(arm_smmuv2, "arm,smmu-v2");

IOMMU_OF_DECLARE(arm_mmu400, "arm,mmu-400", NULL);

IOMMU_OF_DECLARE(arm_mmu400, "arm,mmu-400");

IOMMU_OF_DECLARE(arm_mmu401, "arm,mmu-401", NULL);

IOMMU_OF_DECLARE(arm_mmu401, "arm,mmu-401");

IOMMU_OF_DECLARE(arm_mmu500, "arm,mmu-500", NULL);

IOMMU_OF_DECLARE(arm_mmu500, "arm,mmu-500");

IOMMU_OF_DECLARE(cavium_smmuv2, "cavium,smmu-v2", NULL);

IOMMU_OF_DECLARE(cavium_smmuv2, "cavium,smmu-v2");





MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");

MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");

MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");

MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");

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