Commit ef9303fd authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Vinod Koul
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dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA 



The ZynqMP includes the DisplayPort subsystem with its own DMA engine
called DPDMA. The DPDMA IP comes with 6 individual channels
(4 for display, 2 for audio). This documentation describes DT bindings
of DPDMA.

Signed-off-by: default avatarHyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200717013337.24122-2-laurent.pinchart@ideasonboard.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent b3a9e3b9

Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings



description: |

  These bindings describe the DMA engine included in the Xilinx ZynqMP

  DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3

  channels for a video stream, 1 channel for a graphics stream, and 2 channels

  for an audio stream).



maintainers:

  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>



allOf:

  - $ref: "../dma-controller.yaml#"



properties:

  "#dma-cells":

    const: 1

    description: |

      The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h

      for a list of channel IDs).



  compatible:

    const: xlnx,zynqmp-dpdma



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    description: The AXI clock

    maxItems: 1



  clock-names:

    const: axi_clk



required:

  - "#dma-cells"

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    dma: dma-controller@fd4c0000 {

      compatible = "xlnx,zynqmp-dpdma";

      reg = <0x0 0xfd4c0000 0x0 0x1000>;

      interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;

      interrupt-parent = <&gic>;

      clocks = <&dpdma_clk>;

      clock-names = "axi_clk";

      #dma-cells = <1>;

    };



...

MAINTAINERS

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@@ -18852,6 +18852,14 @@ F: Documentation/devicetree/bindings/media/xilinx/ 
F:	drivers/media/platform/xilinx/

F:	include/uapi/linux/xilinx-v4l2-controls.h













XILINX ZYNQMP DPDMA DRIVER













M:	Hyun Kwon <hyun.kwon@xilinx.com>













M:	Laurent Pinchart <laurent.pinchart@ideasonboard.com>













L:	dmaengine@vger.kernel.org













S:	Supported













F:	Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml













F:	include/dt-bindings/dma/xlnx-zynqmp-dpdma.h



























XILLYBUS DRIVER















M:	Eli Billauer <eli.billauer@gmail.com>















L:	linux-kernel@vger.kernel.org

























include/dt-bindings/dma/xlnx-zynqmp-dpdma.h
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */













/*













 * Copyright 2019 Laurent Pinchart <laurent.pinchart@ideasonboard.com>













 */



























#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__













#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__



























#define ZYNQMP_DPDMA_VIDEO0		0













#define ZYNQMP_DPDMA_VIDEO1		1













#define ZYNQMP_DPDMA_VIDEO2		2













#define ZYNQMP_DPDMA_GRAPHICS		3













#define ZYNQMP_DPDMA_AUDIO0		4













#define ZYNQMP_DPDMA_AUDIO1		5



























#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */


























































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