ARC: [plat-hsdk] use actual clk driver to manage cpu clk (ef833eab) · Commits · 戴 / test

With corresponding clk driver now merged upstream, switch to it. - core_clk now represent the PLL (vs. fixed clk before) - input_clk represent the clk signal src for PLL (basically xtal) Signed-off-by:

Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by:

Vineet Gupta <vgupta@synopsys.com>

arch/arc/boot/dts/hsdk.dts

+9 −2

Original line number	Diff line number	Diff line
		@@ -57,10 +57,10 @@
		};
		};

		core_clk: core-clk {
		input_clk: input-clk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <500000000>;
		clock-frequency = <33333333>;
		};

		cpu_intc: cpu-interrupt-controller {
		@@ -102,6 +102,13 @@

		ranges = <0x00000000 0xf0000000 0x10000000>;

		core_clk: core-clk@0 {
		compatible = "snps,hsdk-core-pll-clock";
		reg = <0x00 0x10>, <0x14B8 0x4>;
		#clock-cells = <0>;
		clocks = <&input_clk>;
		};

		serial: serial@5000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x5000 0x100>;

arch/arc/plat-hsdk/Kconfig

+2 −1

Original line number	Diff line number	Diff line
		@@ -7,3 +7,4 @@

		menuconfig ARC_SOC_HSDK
		bool "ARC HS Development Kit SOC"
		select CLK_HSDK

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