Commit ef78f7b1 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Use drm_gem_object.resv 



Since commit 1ba62714 ("drm: Add reservation_object to
drm_gem_object"), struct drm_gem_object grew its own builtin
reservation_object rendering our own private one bloat. Remove our
redundant reservation_object and point into obj->base.resv instead.

References: 1ba62714 ("drm: Add reservation_object to drm_gem_object")
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190618125858.7295-1-chris@chris-wilson.co.uk
parent 7009db14

drivers/gpu/drm/i915/display/intel_display.c

+3 −3
Original line number Diff line number Diff line
@@ -14256,7 +14256,7 @@ intel_prepare_plane_fb(struct drm_plane *plane, 
		 */

		if (needs_modeset(crtc_state)) {

			ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,

							      old_obj->resv, NULL,

							      old_obj->base.resv, NULL,

							      false, 0,

							      GFP_KERNEL);

			if (ret < 0)
@@ -14300,13 +14300,13 @@ intel_prepare_plane_fb(struct drm_plane *plane, 
		struct dma_fence *fence;



		ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,

						      obj->resv, NULL,

						      obj->base.resv, NULL,

						      false, I915_FENCE_TIMEOUT,

						      GFP_KERNEL);

		if (ret < 0)

			return ret;



		fence = reservation_object_get_excl_rcu(obj->resv);

		fence = reservation_object_get_excl_rcu(obj->base.resv);

		if (fence) {

			add_rps_boost_after_vblank(new_state->crtc, fence);

			dma_fence_put(fence);

drivers/gpu/drm/i915/gem/i915_gem_busy.c

+5 −4
Original line number Diff line number Diff line
@@ -110,13 +110,14 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data, 
	 *

	 */

retry:

	seq = raw_read_seqcount(&obj->resv->seq);

	seq = raw_read_seqcount(&obj->base.resv->seq);



	/* Translate the exclusive fence to the READ *and* WRITE engine */

	args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl));

	args->busy =

		busy_check_writer(rcu_dereference(obj->base.resv->fence_excl));



	/* Translate shared fences to READ set of engines */

	list = rcu_dereference(obj->resv->fence);

	list = rcu_dereference(obj->base.resv->fence);

	if (list) {

		unsigned int shared_count = list->shared_count, i;
@@ -128,7 +129,7 @@ retry: 
		}

	}



	if (args->busy && read_seqcount_retry(&obj->resv->seq, seq))

	if (args->busy && read_seqcount_retry(&obj->base.resv->seq, seq))

		goto retry;



	err = 0;

drivers/gpu/drm/i915/gem/i915_gem_clflush.c

+3 −2
Original line number Diff line number Diff line
@@ -143,11 +143,12 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, 
		dma_fence_get(&clflush->dma);



		i915_sw_fence_await_reservation(&clflush->wait,

						obj->resv, NULL,

						obj->base.resv, NULL,

						true, I915_FENCE_TIMEOUT,

						I915_FENCE_GFP);



		reservation_object_add_excl_fence(obj->resv, &clflush->dma);

		reservation_object_add_excl_fence(obj->base.resv,

						  &clflush->dma);



		i915_sw_fence_commit(&clflush->wait);

	} else if (obj->mm.pages) {

drivers/gpu/drm/i915/gem/i915_gem_client_blt.c

+2 −2
Original line number Diff line number Diff line
@@ -282,13 +282,13 @@ int i915_gem_schedule_fill_pages_blt(struct drm_i915_gem_object *obj, 


	i915_gem_object_lock(obj);

	err = i915_sw_fence_await_reservation(&work->wait,

					      obj->resv, NULL,

					      obj->base.resv, NULL,

					      true, I915_FENCE_TIMEOUT,

					      I915_FENCE_GFP);

	if (err < 0) {

		dma_fence_set_error(&work->dma, err);

	} else {

		reservation_object_add_excl_fence(obj->resv, &work->dma);

		reservation_object_add_excl_fence(obj->base.resv, &work->dma);

		err = 0;

	}

	i915_gem_object_unlock(obj);

drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c

+2 −2
Original line number Diff line number Diff line
@@ -214,7 +214,7 @@ struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 
	exp_info.size = gem_obj->size;

	exp_info.flags = flags;

	exp_info.priv = gem_obj;

	exp_info.resv = obj->resv;

	exp_info.resv = obj->base.resv;



	if (obj->ops->dmabuf_export) {

		int ret = obj->ops->dmabuf_export(obj);
@@ -290,7 +290,7 @@ struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 
	drm_gem_private_object_init(dev, &obj->base, dma_buf->size);

	i915_gem_object_init(obj, &i915_gem_object_dmabuf_ops);

	obj->base.import_attach = attach;

	obj->resv = dma_buf->resv;

	obj->base.resv = dma_buf->resv;



	/* We use GTT as shorthand for a coherent domain, one that is

	 * neither in the GPU cache nor in the CPU cache, where all

CRA Git | Maintained and supported by SUSTech CRA and CCSE