Commit ef42c58a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "This lot provides:

   * Bugfixes for armada irq controller
   * Updates to renesas irq chip
   * Support for the TI-NSPIRE irq controller

  Not strictly a bug fix only pull request, but important updates for
  some of the arm Socs which I completely forgot to send last week.

  Seems like my obliviousness is getting worse, I just can't remember
  when it started"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip: Add support for TI-NSPIRE irqchip
  irqchip: renesas-irqc: Enable mask on suspend
  irqchip: renesas-irqc: Use lazy disable
  irqchip: armada-370-xp: fix MSI race condition
  irqchip: armada-370-xp: fix IPI race condition
parents 1cd731df b6628210

Documentation/devicetree/bindings/interrupt-controller/lsi,zevio-intc.txt

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+18 −0
Original line number Diff line number Diff line 
TI-NSPIRE interrupt controller



Required properties:

- compatible: Compatible property value should be "lsi,zevio-intc".



- reg: Physical base address of the controller and length of memory mapped

	region.



- interrupt-controller : Identifies the node as an interrupt controller



Example:



interrupt-controller {

	compatible = "lsi,zevio-intc";

	interrupt-controller;

	reg = <0xDC000000 0x1000>;

	#interrupt-cells = <1>;

};

drivers/irqchip/Makefile

+1 −0
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@@ -21,6 +21,7 @@ obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o 
obj-$(CONFIG_RENESAS_INTC_IRQPIN)	+= irq-renesas-intc-irqpin.o

obj-$(CONFIG_RENESAS_IRQC)		+= irq-renesas-irqc.o

obj-$(CONFIG_VERSATILE_FPGA_IRQ)	+= irq-versatile-fpga.o

obj-$(CONFIG_ARCH_NSPIRE)		+= irq-zevio.o

obj-$(CONFIG_ARCH_VT8500)		+= irq-vt8500.o

obj-$(CONFIG_TB10X_IRQC)		+= irq-tb10x.o

obj-$(CONFIG_XTENSA)			+= irq-xtensa-pic.o

drivers/irqchip/irq-armada-370-xp.c

+2 −2
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@@ -381,7 +381,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs) 
						ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)

				& PCI_MSI_DOORBELL_MASK;



			writel(~PCI_MSI_DOORBELL_MASK, per_cpu_int_base +

			writel(~msimask, per_cpu_int_base +

			       ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);



			for (msinr = PCI_MSI_DOORBELL_START;
@@ -407,7 +407,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs) 
						ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)

				& IPI_DOORBELL_MASK;



			writel(~IPI_DOORBELL_MASK, per_cpu_int_base +

			writel(~ipimask, per_cpu_int_base +

				ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);



			/* Handle all pending doorbells */

drivers/irqchip/irq-zevio.c

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/*

 *  linux/drivers/irqchip/irq-zevio.c

 *

 *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2, as

 * published by the Free Software Foundation.

 *

 */



#include <linux/io.h>

#include <linux/irq.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>



#include <asm/mach/irq.h>

#include <asm/exception.h>



#include "irqchip.h"



#define IO_STATUS	0x000

#define IO_RAW_STATUS	0x004

#define IO_ENABLE	0x008

#define IO_DISABLE	0x00C

#define IO_CURRENT	0x020

#define IO_RESET	0x028

#define IO_MAX_PRIOTY	0x02C



#define IO_IRQ_BASE	0x000

#define IO_FIQ_BASE	0x100



#define IO_INVERT_SEL	0x200

#define IO_STICKY_SEL	0x204

#define IO_PRIORITY_SEL	0x300



#define MAX_INTRS	32

#define FIQ_START	MAX_INTRS



static struct irq_domain *zevio_irq_domain;

static void __iomem *zevio_irq_io;



static void zevio_irq_ack(struct irq_data *irqd)

{

	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(irqd);

	struct irq_chip_regs *regs =

		&container_of(irqd->chip, struct irq_chip_type, chip)->regs;



	readl(gc->reg_base + regs->ack);

}



static asmlinkage void __exception_irq_entry zevio_handle_irq(struct pt_regs *regs)

{

	int irqnr;



	while (readl(zevio_irq_io + IO_STATUS)) {

		irqnr = readl(zevio_irq_io + IO_CURRENT);

		irqnr = irq_find_mapping(zevio_irq_domain, irqnr);

		handle_IRQ(irqnr, regs);

	};

}



static void __init zevio_init_irq_base(void __iomem *base)

{

	/* Disable all interrupts */

	writel(~0, base + IO_DISABLE);



	/* Accept interrupts of all priorities */

	writel(0xF, base + IO_MAX_PRIOTY);



	/* Reset existing interrupts */

	readl(base + IO_RESET);

}



static int __init zevio_of_init(struct device_node *node,

				struct device_node *parent)

{

	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;

	struct irq_chip_generic *gc;

	int ret;



	if (WARN_ON(zevio_irq_io || zevio_irq_domain))

		return -EBUSY;



	zevio_irq_io = of_iomap(node, 0);

	BUG_ON(!zevio_irq_io);



	/* Do not invert interrupt status bits */

	writel(~0, zevio_irq_io + IO_INVERT_SEL);



	/* Disable sticky interrupts */

	writel(0, zevio_irq_io + IO_STICKY_SEL);



	/* We don't use IRQ priorities. Set each IRQ to highest priority. */

	memset_io(zevio_irq_io + IO_PRIORITY_SEL, 0, MAX_INTRS * sizeof(u32));



	/* Init IRQ and FIQ */

	zevio_init_irq_base(zevio_irq_io + IO_IRQ_BASE);

	zevio_init_irq_base(zevio_irq_io + IO_FIQ_BASE);



	zevio_irq_domain = irq_domain_add_linear(node, MAX_INTRS,

						 &irq_generic_chip_ops, NULL);

	BUG_ON(!zevio_irq_domain);



	ret = irq_alloc_domain_generic_chips(zevio_irq_domain, MAX_INTRS, 1,

					     "zevio_intc", handle_level_irq,

					     clr, 0, IRQ_GC_INIT_MASK_CACHE);

	BUG_ON(ret);



	gc = irq_get_domain_generic_chip(zevio_irq_domain, 0);

	gc->reg_base				= zevio_irq_io;

	gc->chip_types[0].chip.irq_ack		= zevio_irq_ack;

	gc->chip_types[0].chip.irq_mask		= irq_gc_mask_disable_reg;

	gc->chip_types[0].chip.irq_unmask	= irq_gc_unmask_enable_reg;

	gc->chip_types[0].regs.mask		= IO_IRQ_BASE + IO_ENABLE;

	gc->chip_types[0].regs.enable		= IO_IRQ_BASE + IO_ENABLE;

	gc->chip_types[0].regs.disable		= IO_IRQ_BASE + IO_DISABLE;

	gc->chip_types[0].regs.ack		= IO_IRQ_BASE + IO_RESET;



	set_handle_irq(zevio_handle_irq);



	pr_info("TI-NSPIRE classic IRQ controller\n");

	return 0;

}



IRQCHIP_DECLARE(zevio_irq, "lsi,zevio-intc", zevio_of_init);

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