dmaengine: dw: Take HC_LLP flag into account for noLLP auto-config (ef3e515a) · Commits · 戴 / test

Full multi-block transfers functionality is enabled in DW DMA controller only if CHx_MULTI_BLK_EN is set. But LLP-based transfers can be executed only if hardcode channel x LLP register feature isn't enabled, which can be switched on at the IP core synthesis for optimization. If it's enabled then the LLP register is hardcoded to zero, so the blocks chaining based on the LLPs is unsupported. Signed-off-by:

Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by:

Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200723005848.31907-7-Sergey.Semin@baikalelectronics.ru Signed-off-by:

Vinod Koul <vkoul@kernel.org>

drivers/dma/dw/core.c

+10 −1

Original line number	Diff line number	Diff line
		@@ -1178,8 +1178,17 @@ int do_dma_probe(struct dw_dma_chip *chip)
		*/
		dwc->block_size =
		(4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1;

		/*
		* According to the DW DMA databook the true scatter-
		* gether LLPs aren't available if either multi-block
		* config is disabled (CHx_MULTI_BLK_EN == 0) or the
		* LLP register is hard-coded to zeros
		* (CHx_HC_LLP == 1).
		*/
		dwc->nollp =
		(dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
		(dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0 \|\|
		(dwc_params >> DWC_PARAMS_HC_LLP & 0x1) == 1;
		} else {
		dwc->block_size = pdata->block_size;
		dwc->nollp = !pdata->multi_block[i];

drivers/dma/dw/regs.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -125,6 +125,7 @@ struct dw_dma_regs {

		/* Bitfields in DWC_PARAMS */
		#define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */
		#define DWC_PARAMS_HC_LLP 13 /* set LLP register to zero */

		/* bursts size */
		enum dw_dma_msize {

Admin message