ASoC: fsl_sai: Fix Bit Clock Polarity configurations (ef33bc32) · Commits · 戴 / test

The BCP bit in TCR4/RCR4 register rules as followings: 0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. For all formats currently supported in the fsl_sai driver, they're exactly sending data on the falling edge and sampling on the rising edge. However, the driver clears this BCP bit for all of them which results click noise when working with SGTL5000 and big noise with WM8962. Thus this patch corrects the BCP settings for all the formats here to fix the nosie issue. Signed-off-by:

Nicolin Chen <Guangyu.Chen@freescale.com> Acked-by:

Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by:

Mark Brown <broonie@linaro.org>

sound/soc/fsl/fsl_sai.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -179,7 +179,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
		* that is, together with the last bit of the previous
		* data word.
		*/
		val_cr2 &= ~FSL_SAI_CR2_BCP;
		val_cr2 \|= FSL_SAI_CR2_BCP;
		val_cr4 \|= FSL_SAI_CR4_FSE \| FSL_SAI_CR4_FSP;
		break;
		case SND_SOC_DAIFMT_LEFT_J:
		@@ -187,7 +187,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
		* Frame high, one word length for frame sync,
		* frame sync asserts with the first bit of the frame.
		*/
		val_cr2 &= ~FSL_SAI_CR2_BCP;
		val_cr2 \|= FSL_SAI_CR2_BCP;
		val_cr4 &= ~(FSL_SAI_CR4_FSE \| FSL_SAI_CR4_FSP);
		break;
		case SND_SOC_DAIFMT_DSP_A:
		@@ -197,7 +197,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
		* that is, together with the last bit of the previous
		* data word.
		*/
		val_cr2 &= ~FSL_SAI_CR2_BCP;
		val_cr2 \|= FSL_SAI_CR2_BCP;
		val_cr4 &= ~FSL_SAI_CR4_FSP;
		val_cr4 \|= FSL_SAI_CR4_FSE;
		sai->is_dsp_mode = true;
		@@ -207,7 +207,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
		* Frame high, one bit for frame sync,
		* frame sync asserts with the first bit of the frame.
		*/
		val_cr2 &= ~FSL_SAI_CR2_BCP;
		val_cr2 \|= FSL_SAI_CR2_BCP;
		val_cr4 &= ~(FSL_SAI_CR4_FSE \| FSL_SAI_CR4_FSP);
		sai->is_dsp_mode = true;
		break;

Admin message