Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

MPC5121 PSC Device Tree Bindings

PSC in UART mode

----------------

For PSC in UART mode the needed PSC serial devices

are specified by fsl,mpc5121-psc-uart nodes in the

fsl,mpc5121-immr SoC node. Additionally the PSC FIFO

Controller node fsl,mpc5121-psc-fifo is requered there:

fsl,mpc5121-psc-uart nodes

--------------------------

Required properties :

 - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc"

 - cell-index : Index of the PSC in hardware

 - reg : Offset and length of the register set for the PSC device

 - interrupts : <a b> where a is the interrupt number of the

   PSC FIFO Controller and b is a field that represents an

   encoding of the sense and level information for the interrupt.

 - interrupt-parent : the phandle for the interrupt controller that

   services interrupts for this device.

Recommended properties :

 - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)

 - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)

fsl,mpc5121-psc-fifo node

-------------------------

Required properties :

 - compatible : Should be "fsl,mpc5121-psc-fifo"

 - reg : Offset and length of the register set for the PSC

         FIFO Controller

 - interrupts : <a b> where a is the interrupt number of the

   PSC FIFO Controller and b is a field that represents an

   encoding of the sense and level information for the interrupt.

 - interrupt-parent : the phandle for the interrupt controller that

   services interrupts for this device.

Example for a board using PSC0 and PSC1 devices in serial mode:

serial@11000 {

	compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";

	cell-index = <0>;

	reg = <0x11000 0x100>;

	interrupts = <40 0x8>;

	interrupt-parent = < &ipic >;

	fsl,rx-fifo-size = <16>;

	fsl,tx-fifo-size = <16>;

};

serial@11100 {

	compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";

	cell-index = <1>;

	reg = <0x11100 0x100>;

	interrupts = <40 0x8>;

	interrupt-parent = < &ipic >;

	fsl,rx-fifo-size = <16>;

	fsl,tx-fifo-size = <16>;

};

pscfifo@11f00 {

	compatible = "fsl,mpc5121-psc-fifo";

	reg = <0x11f00 0x100>;

	interrupts = <40 0x8>;

	interrupt-parent = < &ipic >;

};

- interrupt-parent : the phandle for the interrupt controller that

  services interrupts for this device.

Optional properties:

- gpios : specifies the gpio pins to be used for chipselects.

  The gpios will be referred to as reg = <index> in the SPI child nodes.

  If unspecified, a single SPI device without a chip select can be used.

Example:

	spi@4c0 {

		cell-index = <0>;

		interrupts = <82 0>;

		interrupt-parent = <700>;

		mode = "cpu";

		gpios = <&gpio 18 1	// device reg=<0>

			 &gpio 19 1>;	// device reg=<1>

	};

GDB intends to support the following hardware debug features of BookE

processors:

4 hardware breakpoints (IAC)

2 hardware watchpoints (read, write and read-write) (DAC)

2 value conditions for the hardware watchpoints (DVC)

For that, we need to extend ptrace so that GDB can query and set these

resources. Since we're extending, we're trying to create an interface

that's extendable and that covers both BookE and server processors, so

that GDB doesn't need to special-case each of them. We added the

following 3 new ptrace requests.

1. PTRACE_PPC_GETHWDEBUGINFO

Query for GDB to discover the hardware debug features. The main info to

be returned here is the minimum alignment for the hardware watchpoints.

BookE processors don't have restrictions here, but server processors have

an 8-byte alignment restriction for hardware watchpoints. We'd like to avoid

adding special cases to GDB based on what it sees in AUXV.

Since we're at it, we added other useful info that the kernel can return to

GDB: this query will return the number of hardware breakpoints, hardware

watchpoints and whether it supports a range of addresses and a condition.

The query will fill the following structure provided by the requesting process:

struct ppc_debug_info {

       unit32_t version;

       unit32_t num_instruction_bps;

       unit32_t num_data_bps;

       unit32_t num_condition_regs;

       unit32_t data_bp_alignment;

       unit32_t sizeof_condition; /* size of the DVC register */

       uint64_t features; /* bitmask of the individual flags */

};

features will have bits indicating whether there is support for:

#define PPC_DEBUG_FEATURE_INSN_BP_RANGE		0x1

#define PPC_DEBUG_FEATURE_INSN_BP_MASK		0x2

#define PPC_DEBUG_FEATURE_DATA_BP_RANGE		0x4

#define PPC_DEBUG_FEATURE_DATA_BP_MASK		0x8

2. PTRACE_SETHWDEBUG

Sets a hardware breakpoint or watchpoint, according to the provided structure:

struct ppc_hw_breakpoint {

        uint32_t version;

#define PPC_BREAKPOINT_TRIGGER_EXECUTE  0x1

#define PPC_BREAKPOINT_TRIGGER_READ     0x2

#define PPC_BREAKPOINT_TRIGGER_WRITE    0x4

        uint32_t trigger_type;       /* only some combinations allowed */

#define PPC_BREAKPOINT_MODE_EXACT               0x0

#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE     0x1

#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE     0x2

#define PPC_BREAKPOINT_MODE_MASK                0x3

        uint32_t addr_mode;          /* address match mode */

#define PPC_BREAKPOINT_CONDITION_MODE   0x3

#define PPC_BREAKPOINT_CONDITION_NONE   0x0

#define PPC_BREAKPOINT_CONDITION_AND    0x1

#define PPC_BREAKPOINT_CONDITION_EXACT  0x1	/* different name for the same thing as above */

#define PPC_BREAKPOINT_CONDITION_OR     0x2

#define PPC_BREAKPOINT_CONDITION_AND_OR 0x3

#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000	/* byte enable bits */

#define PPC_BREAKPOINT_CONDITION_BE(n)  (1<<((n)+16))

        uint32_t condition_mode;     /* break/watchpoint condition flags */

        uint64_t addr;

        uint64_t addr2;

        uint64_t condition_value;

};

A request specifies one event, not necessarily just one register to be set.

For instance, if the request is for a watchpoint with a condition, both the

DAC and DVC registers will be set in the same request.

With this GDB can ask for all kinds of hardware breakpoints and watchpoints

that the BookE supports. COMEFROM breakpoints available in server processors

are not contemplated, but that is out of the scope of this work.

ptrace will return an integer (handle) uniquely identifying the breakpoint or

watchpoint just created. This integer will be used in the PTRACE_DELHWDEBUG

request to ask for its removal. Return -ENOSPC if the requested breakpoint

can't be allocated on the registers.

Some examples of using the structure to:

- set a breakpoint in the first breakpoint register

  p.version         = PPC_DEBUG_CURRENT_VERSION;

  p.trigger_type    = PPC_BREAKPOINT_TRIGGER_EXECUTE;

  p.addr_mode       = PPC_BREAKPOINT_MODE_EXACT;

  p.condition_mode  = PPC_BREAKPOINT_CONDITION_NONE;

  p.addr            = (uint64_t) address;

  p.addr2           = 0;

  p.condition_value = 0;

- set a watchpoint which triggers on reads in the second watchpoint register

  p.version         = PPC_DEBUG_CURRENT_VERSION;

  p.trigger_type    = PPC_BREAKPOINT_TRIGGER_READ;

  p.addr_mode       = PPC_BREAKPOINT_MODE_EXACT;

  p.condition_mode  = PPC_BREAKPOINT_CONDITION_NONE;

  p.addr            = (uint64_t) address;

  p.addr2           = 0;

  p.condition_value = 0;

- set a watchpoint which triggers only with a specific value

  p.version         = PPC_DEBUG_CURRENT_VERSION;

  p.trigger_type    = PPC_BREAKPOINT_TRIGGER_READ;

  p.addr_mode       = PPC_BREAKPOINT_MODE_EXACT;

  p.condition_mode  = PPC_BREAKPOINT_CONDITION_AND | PPC_BREAKPOINT_CONDITION_BE_ALL;

  p.addr            = (uint64_t) address;

  p.addr2           = 0;

  p.condition_value = (uint64_t) condition;

- set a ranged hardware breakpoint

  p.version         = PPC_DEBUG_CURRENT_VERSION;

  p.trigger_type    = PPC_BREAKPOINT_TRIGGER_EXECUTE;

  p.addr_mode       = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;

  p.condition_mode  = PPC_BREAKPOINT_CONDITION_NONE;

  p.addr            = (uint64_t) begin_range;

  p.addr2           = (uint64_t) end_range;

  p.condition_value = 0;

3. PTRACE_DELHWDEBUG

Takes an integer which identifies an existing breakpoint or watchpoint

(i.e., the value returned from PTRACE_SETHWDEBUG), and deletes the

corresponding breakpoint or watchpoint..

config NR_IRQS

	int "Number of virtual interrupt numbers"

	range 32 512

	range 32 32768

	default "512"

	help

	  This defines the number of virtual interrupt numbers the kernel

config ARCH_SUPPORTS_DEBUG_PAGEALLOC

	def_bool y

config PPC_ADV_DEBUG_REGS

	bool

	depends on 40x || BOOKE

	default y

config PPC_ADV_DEBUG_IACS

	int

	depends on PPC_ADV_DEBUG_REGS

	default 4 if 44x

	default 2

config PPC_ADV_DEBUG_DACS

	int

	depends on PPC_ADV_DEBUG_REGS

	default 2

config PPC_ADV_DEBUG_DVCS

	int

	depends on PPC_ADV_DEBUG_REGS

	default 2 if 44x

	default 0

config PPC_ADV_DEBUG_DAC_RANGE

	bool

	depends on PPC_ADV_DEBUG_REGS && 44x

	default y

source "init/Kconfig"

source "kernel/Kconfig.freezer"

			d-cache-size = <32768>;

			dcr-controller;

			dcr-access-method = "native";

			next-level-cache = <&L2C0>;

		};

	};

			dcr-reg = <0x010 0x002>;

		};

		CRYPTO: crypto@180000 {

			compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";

			reg = <4 0x00180000 0x80400>;

			interrupt-parent = <&UIC0>;

			interrupts = <0x1d 0x4>;

		};

		MAL0: mcmal {

			compatible = "ibm,mcmal-460gt", "ibm,mcmal2";

			dcr-reg = <0x180 0x062>;

				max-frame-size = <9000>;

				rx-fifo-size = <4096>;

				tx-fifo-size = <2048>;

				rx-fifo-size-gige = <16384>;

				phy-mode = "sgmii";

				phy-map = <0xffffffff>;

				gpcs-address = <0x0000000a>;

				max-frame-size = <9000>;

				rx-fifo-size = <4096>;

				tx-fifo-size = <2048>;

				rx-fifo-size-gige = <16384>;

				phy-mode = "sgmii";

				phy-map = <0x00000000>;

				gpcs-address = <0x0000000b>;

				max-frame-size = <9000>;

				rx-fifo-size = <4096>;

				tx-fifo-size = <2048>;

				rx-fifo-size-gige = <16384>;

				tx-fifo-size-gige = <16384>; /* emac2&3 only */

				phy-mode = "sgmii";

				phy-map = <0x00000001>;

				gpcs-address = <0x0000000C>;