Commit ef0ac9f2 authored by Grzegorz Jaszczyk's avatar Grzegorz Jaszczyk Committed by Kishon Vijay Abraham I
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phy: mvebu-cp110-comphy: Add SATA support 



Add the corresponding entries in the COMPHY modes table.

SATA support does not need any additional care.

Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
[miquel.raynal@bootlin.com: adapt the content to the mainline driver]
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent c527a636

drivers/phy/marvell/phy-mvebu-cp110-comphy.c

+10 −0
Original line number Diff line number Diff line
@@ -155,6 +155,7 @@ 
#define COMPHY_FW_PARAM_ETH(mode, port, speed)				\

	COMPHY_FW_PARAM_FULL(mode, port, speed, 0)



#define COMPHY_FW_MODE_SATA		0x1

#define COMPHY_FW_MODE_SGMII		0x2 /* SGMII 1G */

#define COMPHY_FW_MODE_HS_SGMII		0x3 /* SGMII 2.5G */

#define COMPHY_FW_MODE_USB3H		0x4
@@ -195,9 +196,11 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = { 
	/* lane 0 */

	ETH_CONF(0, 1, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),

	ETH_CONF(0, 1, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),

	GEN_CONF(0, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),

	/* lane 1 */

	GEN_CONF(1, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),

	GEN_CONF(1, 0, PHY_MODE_USB_DEVICE_SS, COMPHY_FW_MODE_USB3D),

	GEN_CONF(1, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),

	ETH_CONF(1, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),

	ETH_CONF(1, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),

	/* lane 2 */
@@ -206,11 +209,13 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = { 
	ETH_CONF(2, 0, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),

	ETH_CONF(2, 0, PHY_INTERFACE_MODE_10GKR, 0x1, COMPHY_FW_MODE_XFI),

	GEN_CONF(2, 0, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),

	GEN_CONF(2, 0, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),

	/* lane 3 */

	ETH_CONF(3, 1, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),

	ETH_CONF(3, 1, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),

	ETH_CONF(3, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),

	GEN_CONF(3, 1, PHY_MODE_USB_HOST_SS, COMPHY_FW_MODE_USB3H),

	GEN_CONF(3, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),

	/* lane 4 */

	ETH_CONF(4, 0, PHY_INTERFACE_MODE_SGMII, 0x2, COMPHY_FW_MODE_SGMII),

	ETH_CONF(4, 0, PHY_INTERFACE_MODE_2500BASEX, 0x2, COMPHY_FW_MODE_HS_SGMII),
@@ -223,6 +228,7 @@ static const struct mvebu_comphy_conf mvebu_comphy_cp110_modes[] = { 
	ETH_CONF(4, 1, PHY_INTERFACE_MODE_10GKR, -1, COMPHY_FW_MODE_XFI),

	/* lane 5 */

	ETH_CONF(5, 1, PHY_INTERFACE_MODE_RXAUI, -1, COMPHY_FW_MODE_RXAUI),

	GEN_CONF(5, 1, PHY_MODE_SATA, COMPHY_FW_MODE_SATA),

	ETH_CONF(5, 2, PHY_INTERFACE_MODE_SGMII, 0x1, COMPHY_FW_MODE_SGMII),

	ETH_CONF(5, 2, PHY_INTERFACE_MODE_2500BASEX, 0x1, COMPHY_FW_MODE_HS_SGMII),

};
@@ -666,6 +672,10 @@ static int mvebu_comphy_power_on(struct phy *phy) 
		dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id);

		fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);

		break;

	case PHY_MODE_SATA:

		dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id);

		fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);

		break;

	default:

		dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);

		return -ENOTSUPP;

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