Commit eeedcea6 authored Jun 26, 2015 by Geert Uytterhoeven Committed by Russell King Jul 10, 2015

ARM: 8395/1: l2c: Add support for the "arm,shared-override" property



"CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
Shareable attribute" states:

    "The default behavior of the cache controller with respect to the
     shareable attribute is to transform Normal Memory Non-cacheable
     transactions into:
        - cacheable no allocate for reads
        - write through no write allocate for writes."

Depending on the system architecture, this may cause memory corruption
in the presence of bus mastering devices (e.g. OHCI). To avoid such
corruption, the default behavior can be disabled by setting the Shared
Override bit in the Auxiliary Control register.

Currently the Shared Override bit can be set only using C code:
  - by calling l2x0_init() directly, which is deprecated,
  - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
    fields, but using values differing from 0/~0 is also deprecated.

Hence add support for an "arm,shared-override" device tree property for
the l2c device node. By specifying this property, affected systems can
indicate that non-cacheable transactions must not be transformed.
Then, it's up to the OS to decide. The current behavior is to set the
"shared attribute override enable" bit, as there may exist kernel linear
mappings and cacheable aliases for the DMA buffers, even if CMA is
enabled.

See also commit 1a8e41cd ("ARM: 6395/1: VExpress: Set bit 22 in
the PL310 (cache controller) AuxCtlr register"):

    "Clearing bit 22 in the PL310 Auxiliary Control register (shared
     attribute override enable) has the side effect of transforming
     Normal Shared Non-cacheable reads into Cacheable no-allocate reads.

     Coherent DMA buffers in Linux always have a Cacheable alias via the
     kernel linear mapping and the processor can speculatively load
     cache lines into the PL310 controller. With bit 22 cleared,
     Non-cacheable reads would unexpectedly hit such cache lines leading
     to buffer corruption."

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

parent d770e558

Documentation/devicetree/bindings/arm/l2cc.txt

+6 −0

Original line number	Diff line number	Diff line
		@@ -67,6 +67,12 @@ Optional properties:
		disable if zero.
		- arm,prefetch-offset : Override prefetch offset value. Valid values are
		0-7, 15, 23, and 31.
		- arm,shared-override : The default behavior of the pl310 cache controller with
		respect to the shareable attribute is to transform "normal memory
		non-cacheable transactions" into "cacheable no allocate" (for reads) or
		"write through no write allocate" (for writes).
		On systems where this may cause DMA buffer corruption, this property must be
		specified to indicate that such transforms are precluded.
		- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1>
		(forcibly enable), property absent (retain settings set by firmware)
		- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),

arch/arm/mm/cache-l2x0.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -1171,6 +1171,11 @@ static void __init l2c310_of_parse(const struct device_node *np,
		}
		}

		if (of_property_read_bool(np, "arm,shared-override")) {
		*aux_val \|= L2C_AUX_CTRL_SHARED_OVERRIDE;
		*aux_mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE;
		}

		prefetch = l2x0_saved_regs.prefetch_ctrl;

		ret = of_property_read_u32(np, "arm,double-linefill", &val);

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