arm64: cpufeature: Group indexed system register definitions by name (eeb2d87e) · Commits · 戴 / test

Some system registers contain an index in the name (e.g. ID_MMFR<n>_EL1) and, while this index often follows the register encoding, newer additions to the architecture are necessarily tacked on the end. Sorting these registers by encoding therefore becomes a bit of a mess. Group the indexed system register definitions by name so that it's easier to read and will hopefully reduce the chance of us accidentally introducing duplicate definitions in the future. Acked-by:

Mark Rutland <mark.rutland@arm.com> Signed-off-by:

Will Deacon <will@kernel.org>

arch/arm64/include/asm/sysreg.h

+5 −1

Original line number	Diff line number	Diff line
		@@ -105,6 +105,10 @@
		#define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
		#define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)

		/*
		* System registers, organised loosely by encoding but grouped together
		* where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
		*/
		#define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
		#define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
		#define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
		@@ -140,6 +144,7 @@
		#define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
		#define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
		#define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
		#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)

		#define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
		#define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
		@@ -147,7 +152,6 @@
		#define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
		#define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
		#define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
		#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
		#define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7)

		#define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)

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