Merge branch 'pci/misc'

through the Memory-mapped Remote Procedure Call (MRPC) interface.

Commands are submitted to the interface with a 4-byte command

identifier and up to 1KB of command specific data. The firmware will

respond with a 4 bytes return code and up to 1KB of command specific

respond with a 4-byte return code and up to 1KB of command-specific

data. The interface only processes a single command at a time.

The char device has the following semantics:

* A write must consist of at least 4 bytes and no more than 1028 bytes.

  The first four bytes will be interpreted as the command to run and

  the remainder will be used as the input data. A write will send the

  The first 4 bytes will be interpreted as the Command ID and the

  remainder will be used as the input data. A write will send the

  command to the firmware to begin processing.

* Each write must be followed by exactly one read. Any double write will

  produce an error.

* A read will block until the firmware completes the command and return

  the four bytes of status plus up to 1024 bytes of output data. (The

  length will be specified by the size parameter of the read call --

  reading less than 4 bytes will produce an error.

  the 4-byte Command Return Value plus up to 1024 bytes of output

  data. (The length will be specified by the size parameter of the read

  call -- reading less than 4 bytes will produce an error.)

* The poll call will also be supported for userspace applications that

  need to do other things while waiting for the command to complete.

Non-Transparent Bridge (NTB) Driver

===================================

An NTB driver is provided for the switchtec hardware in switchtec_ntb.

Currently, it only supports switches configured with exactly 2

partitions. It also requires the following configuration settings:

An NTB hardware driver is provided for the Switchtec hardware in

ntb_hw_switchtec. Currently, it only supports switches configured with

exactly 2 NT partitions and zero or more non-NT partitions. It also requires

the following configuration settings:

* Both partitions must be able to access each other's GAS spaces.

* Both NT partitions must be able to access each other's GAS spaces.

  Thus, the bits in the GAS Access Vector under Management Settings

  must be set to support this.

* Kernel configuration MUST include support for NTB (CONFIG_NTB needs

  to be set)

NT EP BAR 2 will be dynamically configured as a Direct Window, and

the configuration file does not need to configure it explicitly.

Please refer to Documentation/ntb.txt in Linux source tree for an overall

understanding of the Linux NTB stack. ntb_hw_switchtec works as an NTB

Hardware Driver in this stack.

	 * like others but it will lock up the whole machine HARD if

	 * 65536 byte PRD entry is fed. Reduce maximum segment size.

	 */

	rc = pci_set_dma_max_seg_size(pdev, 65536 - 512);

	rc = dma_set_max_seg_size(&pdev->dev, 65536 - 512);

	if (rc) {

		dev_err(&pdev->dev, "failed to set the maximum segment size\n");

		return rc;

		goto failed_enable;

	pci_set_master(dev);

	pci_set_dma_max_seg_size(dev, RSXX_HW_BLK_SIZE);

	dma_set_max_seg_size(&dev->dev, RSXX_HW_BLK_SIZE);

	st = pci_set_dma_mask(dev, DMA_BIT_MASK(64));

	if (st) {

static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)

{

	dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,

			  pci_unmap_addr(sq, mapping));

			  dma_unmap_addr(sq, mapping));

}

static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)

	if (!sq->queue)

		return -ENOMEM;

	sq->phys_addr = virt_to_phys(sq->queue);

	pci_unmap_addr_set(sq, mapping, sq->dma_addr);

	dma_unmap_addr_set(sq, mapping, sq->dma_addr);

	return 0;

}

	dma_free_coherent(&rdev->lldi.pdev->dev,

			  wq->memsize, wq->queue,

			pci_unmap_addr(wq, mapping));

			dma_unmap_addr(wq, mapping));

	c4iw_rqtpool_free(rdev, wq->rqt_hwaddr, wq->rqt_size);

	kfree(wq->sw_rq);

	c4iw_put_qpid(rdev, wq->qid, uctx);

		goto err_free_rqtpool;

	memset(wq->queue, 0, wq->memsize);

	pci_unmap_addr_set(wq, mapping, wq->dma_addr);

	dma_unmap_addr_set(wq, mapping, wq->dma_addr);

	wq->bar2_va = c4iw_bar2_addrs(rdev, wq->qid, T4_BAR2_QTYPE_EGRESS,

				      &wq->bar2_qid,

err_free_queue:

	dma_free_coherent(&rdev->lldi.pdev->dev,

			  wq->memsize, wq->queue,

			pci_unmap_addr(wq, mapping));

			dma_unmap_addr(wq, mapping));

err_free_rqtpool:

	c4iw_rqtpool_free(rdev, wq->rqt_hwaddr, wq->rqt_size);

err_free_pending_wrs:

struct t4_srq {

	union t4_recv_wr *queue;

	dma_addr_t dma_addr;

	DECLARE_PCI_UNMAP_ADDR(mapping);

	DEFINE_DMA_UNMAP_ADDR(mapping);

	struct t4_swrqe *sw_rq;

	void __iomem *bar2_va;

	u64 bar2_pa;