iavf: diet and reformat (ee61022a) · Commits · 戴 / test

drivers/net/ethernet/intel/iavf/i40e_adminq.c

+0 −27

Original line number	Diff line number	Diff line
		@@ -7,16 +7,6 @@
		#include "i40e_adminq.h"
		#include "i40e_prototype.h"

		/**
		* i40e_is_nvm_update_op - return true if this is an NVM update operation
		* @desc: API request descriptor
		**/
		static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc)
		{
		return (desc->opcode == i40e_aqc_opc_nvm_erase) \|\|
		(desc->opcode == i40e_aqc_opc_nvm_update);
		}

		/**
		* i40e_adminq_init_regs - Initialize AdminQ registers
		* @hw: pointer to the hardware structure
		@@ -569,9 +559,6 @@ i40e_status i40evf_shutdown_adminq(struct i40e_hw *hw)
		i40e_shutdown_asq(hw);
		i40e_shutdown_arq(hw);

		if (hw->nvm_buff.va)
		i40e_free_virt_mem(hw, &hw->nvm_buff);

		return ret_code;
		}

		@@ -951,17 +938,3 @@ clean_arq_element_err:

		return ret_code;
		}

		void i40evf_resume_aq(struct i40e_hw *hw)
		{
		/* Registers are reset after PF reset */
		hw->aq.asq.next_to_use = 0;
		hw->aq.asq.next_to_clean = 0;

		i40e_config_asq_regs(hw);

		hw->aq.arq.next_to_use = 0;
		hw->aq.arq.next_to_clean = 0;

		i40e_config_arq_regs(hw);
		}

drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h

+44 −2233

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/intel/iavf/i40e_common.c

+0 −338

Original line number	Diff line number	Diff line
		@@ -525,7 +525,6 @@ i40e_status i40evf_aq_set_rss_key(struct i40e_hw *hw,
		return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
		}


		/* The i40evf_ptype_lookup table is used to convert from the 8-bit ptype in the
		* hardware to a bit-field that can be used by SW to more easily determine the
		* packet type.
		@@ -891,135 +890,6 @@ struct i40e_rx_ptype_decoded i40evf_ptype_lookup[] = {
		I40E_PTT_UNUSED_ENTRY(255)
		};

		/**
		* i40evf_aq_rx_ctl_read_register - use FW to read from an Rx control register
		* @hw: pointer to the hw struct
		* @reg_addr: register address
		* @reg_val: ptr to register value
		* @cmd_details: pointer to command details structure or NULL
		*
		* Use the firmware to read the Rx control register,
		* especially useful if the Rx unit is under heavy pressure
		**/
		i40e_status i40evf_aq_rx_ctl_read_register(struct i40e_hw *hw,
		u32 reg_addr, u32 *reg_val,
		struct i40e_asq_cmd_details *cmd_details)
		{
		struct i40e_aq_desc desc;
		struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
		(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
		i40e_status status;

		if (!reg_val)
		return I40E_ERR_PARAM;

		i40evf_fill_default_direct_cmd_desc(&desc,
		i40e_aqc_opc_rx_ctl_reg_read);

		cmd_resp->address = cpu_to_le32(reg_addr);

		status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);

		if (status == 0)
		*reg_val = le32_to_cpu(cmd_resp->value);

		return status;
		}

		/**
		* i40evf_read_rx_ctl - read from an Rx control register
		* @hw: pointer to the hw struct
		* @reg_addr: register address
		**/
		u32 i40evf_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
		{
		i40e_status status = 0;
		bool use_register;
		int retry = 5;
		u32 val = 0;

		use_register = (((hw->aq.api_maj_ver == 1) &&
		(hw->aq.api_min_ver < 5)) \|\|
		(hw->mac.type == I40E_MAC_X722));
		if (!use_register) {
		do_retry:
		status = i40evf_aq_rx_ctl_read_register(hw, reg_addr,
		&val, NULL);
		if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
		usleep_range(1000, 2000);
		retry--;
		goto do_retry;
		}
		}

		/* if the AQ access failed, try the old-fashioned way */
		if (status \|\| use_register)
		val = rd32(hw, reg_addr);

		return val;
		}

		/**
		* i40evf_aq_rx_ctl_write_register
		* @hw: pointer to the hw struct
		* @reg_addr: register address
		* @reg_val: register value
		* @cmd_details: pointer to command details structure or NULL
		*
		* Use the firmware to write to an Rx control register,
		* especially useful if the Rx unit is under heavy pressure
		**/
		i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw,
		u32 reg_addr, u32 reg_val,
		struct i40e_asq_cmd_details *cmd_details)
		{
		struct i40e_aq_desc desc;
		struct i40e_aqc_rx_ctl_reg_read_write *cmd =
		(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
		i40e_status status;

		i40evf_fill_default_direct_cmd_desc(&desc,
		i40e_aqc_opc_rx_ctl_reg_write);

		cmd->address = cpu_to_le32(reg_addr);
		cmd->value = cpu_to_le32(reg_val);

		status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);

		return status;
		}

		/**
		* i40evf_write_rx_ctl - write to an Rx control register
		* @hw: pointer to the hw struct
		* @reg_addr: register address
		* @reg_val: register value
		**/
		void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
		{
		i40e_status status = 0;
		bool use_register;
		int retry = 5;

		use_register = (((hw->aq.api_maj_ver == 1) &&
		(hw->aq.api_min_ver < 5)) \|\|
		(hw->mac.type == I40E_MAC_X722));
		if (!use_register) {
		do_retry:
		status = i40evf_aq_rx_ctl_write_register(hw, reg_addr,
		reg_val, NULL);
		if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
		usleep_range(1000, 2000);
		retry--;
		goto do_retry;
		}
		}

		/* if the AQ access failed, try the old-fashioned way */
		if (status \|\| use_register)
		wr32(hw, reg_addr, reg_val);
		}

		/**
		* i40e_aq_send_msg_to_pf
		* @hw: pointer to the hardware structure
		@@ -1110,211 +980,3 @@ i40e_status i40e_vf_reset(struct i40e_hw *hw)
		return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
		0, NULL, 0, NULL);
		}

		/**
		* i40evf_aq_write_ddp - Write dynamic device personalization (ddp)
		* @hw: pointer to the hw struct
		* @buff: command buffer (size in bytes = buff_size)
		* @buff_size: buffer size in bytes
		* @track_id: package tracking id
		* @error_offset: returns error offset
		* @error_info: returns error information
		* @cmd_details: pointer to command details structure or NULL
		**/
		enum
		i40e_status_code i40evf_aq_write_ddp(struct i40e_hw hw, void buff,
		u16 buff_size, u32 track_id,
		u32 error_offset, u32 error_info,
		struct i40e_asq_cmd_details *cmd_details)
		{
		struct i40e_aq_desc desc;
		struct i40e_aqc_write_personalization_profile *cmd =
		(struct i40e_aqc_write_personalization_profile *)
		&desc.params.raw;
		struct i40e_aqc_write_ddp_resp *resp;
		i40e_status status;

		i40evf_fill_default_direct_cmd_desc(&desc,
		i40e_aqc_opc_write_personalization_profile);

		desc.flags \|= cpu_to_le16(I40E_AQ_FLAG_BUF \| I40E_AQ_FLAG_RD);
		if (buff_size > I40E_AQ_LARGE_BUF)
		desc.flags \|= cpu_to_le16((u16)I40E_AQ_FLAG_LB);

		desc.datalen = cpu_to_le16(buff_size);

		cmd->profile_track_id = cpu_to_le32(track_id);

		status = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
		if (!status) {
		resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
		if (error_offset)
		*error_offset = le32_to_cpu(resp->error_offset);
		if (error_info)
		*error_info = le32_to_cpu(resp->error_info);
		}

		return status;
		}

		/**
		* i40evf_aq_get_ddp_list - Read dynamic device personalization (ddp)
		* @hw: pointer to the hw struct
		* @buff: command buffer (size in bytes = buff_size)
		* @buff_size: buffer size in bytes
		* @flags: AdminQ command flags
		* @cmd_details: pointer to command details structure or NULL
		**/
		enum
		i40e_status_code i40evf_aq_get_ddp_list(struct i40e_hw hw, void buff,
		u16 buff_size, u8 flags,
		struct i40e_asq_cmd_details *cmd_details)
		{
		struct i40e_aq_desc desc;
		struct i40e_aqc_get_applied_profiles *cmd =
		(struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
		i40e_status status;

		i40evf_fill_default_direct_cmd_desc(&desc,
		i40e_aqc_opc_get_personalization_profile_list);

		desc.flags \|= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
		if (buff_size > I40E_AQ_LARGE_BUF)
		desc.flags \|= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
		desc.datalen = cpu_to_le16(buff_size);

		cmd->flags = flags;

		status = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);

		return status;
		}

		/**
		* i40evf_find_segment_in_package
		* @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
		* @pkg_hdr: pointer to the package header to be searched
		*
		* This function searches a package file for a particular segment type. On
		* success it returns a pointer to the segment header, otherwise it will
		* return NULL.
		**/
		struct i40e_generic_seg_header *
		i40evf_find_segment_in_package(u32 segment_type,
		struct i40e_package_header *pkg_hdr)
		{
		struct i40e_generic_seg_header *segment;
		u32 i;

		/* Search all package segments for the requested segment type */
		for (i = 0; i < pkg_hdr->segment_count; i++) {
		segment =
		(struct i40e_generic_seg_header )((u8 )pkg_hdr +
		pkg_hdr->segment_offset[i]);

		if (segment->type == segment_type)
		return segment;
		}

		return NULL;
		}

		/**
		* i40evf_write_profile
		* @hw: pointer to the hardware structure
		* @profile: pointer to the profile segment of the package to be downloaded
		* @track_id: package tracking id
		*
		* Handles the download of a complete package.
		*/
		enum i40e_status_code
		i40evf_write_profile(struct i40e_hw hw, struct i40e_profile_segment profile,
		u32 track_id)
		{
		i40e_status status = 0;
		struct i40e_section_table *sec_tbl;
		struct i40e_profile_section_header *sec = NULL;
		u32 dev_cnt;
		u32 vendor_dev_id;
		u32 *nvm;
		u32 section_size = 0;
		u32 offset = 0, info = 0;
		u32 i;

		dev_cnt = profile->device_table_count;

		for (i = 0; i < dev_cnt; i++) {
		vendor_dev_id = profile->device_table[i].vendor_dev_id;
		if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL)
		if (hw->device_id == (vendor_dev_id & 0xFFFF))
		break;
		}
		if (i == dev_cnt) {
		i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
		return I40E_ERR_DEVICE_NOT_SUPPORTED;
		}

		nvm = (u32 *)&profile->device_table[dev_cnt];
		sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];

		for (i = 0; i < sec_tbl->section_count; i++) {
		sec = (struct i40e_profile_section_header )((u8 )profile +
		sec_tbl->section_offset[i]);

		/* Skip 'AQ', 'note' and 'name' sections */
		if (sec->section.type != SECTION_TYPE_MMIO)
		continue;

		section_size = sec->section.size +
		sizeof(struct i40e_profile_section_header);

		/* Write profile */
		status = i40evf_aq_write_ddp(hw, (void *)sec, (u16)section_size,
		track_id, &offset, &info, NULL);
		if (status) {
		i40e_debug(hw, I40E_DEBUG_PACKAGE,
		"Failed to write profile: offset %d, info %d",
		offset, info);
		break;
		}
		}
		return status;
		}

		/**
		* i40evf_add_pinfo_to_list
		* @hw: pointer to the hardware structure
		* @profile: pointer to the profile segment of the package
		* @profile_info_sec: buffer for information section
		* @track_id: package tracking id
		*
		* Register a profile to the list of loaded profiles.
		*/
		enum i40e_status_code
		i40evf_add_pinfo_to_list(struct i40e_hw *hw,
		struct i40e_profile_segment *profile,
		u8 *profile_info_sec, u32 track_id)
		{
		i40e_status status = 0;
		struct i40e_profile_section_header *sec = NULL;
		struct i40e_profile_info *pinfo;
		u32 offset = 0, info = 0;

		sec = (struct i40e_profile_section_header *)profile_info_sec;
		sec->tbl_size = 1;
		sec->data_end = sizeof(struct i40e_profile_section_header) +
		sizeof(struct i40e_profile_info);
		sec->section.type = SECTION_TYPE_INFO;
		sec->section.offset = sizeof(struct i40e_profile_section_header);
		sec->section.size = sizeof(struct i40e_profile_info);
		pinfo = (struct i40e_profile_info *)(profile_info_sec +
		sec->section.offset);
		pinfo->track_id = track_id;
		pinfo->version = profile->version;
		pinfo->op = I40E_DDP_ADD_TRACKID;
		memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);

		status = i40evf_aq_write_ddp(hw, (void *)sec, sec->data_end,
		track_id, &offset, &info, NULL);
		return status;
		}

drivers/net/ethernet/intel/iavf/i40e_hmc.h

deleted100644 → 0

+0 −215

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0 */
		/* Copyright(c) 2013 - 2018 Intel Corporation. */

		#ifndef _I40E_HMC_H_
		#define _I40E_HMC_H_

		#define I40E_HMC_MAX_BP_COUNT 512

		/* forward-declare the HW struct for the compiler */
		struct i40e_hw;

		#define I40E_HMC_INFO_SIGNATURE 0x484D5347 /* HMSG */
		#define I40E_HMC_PD_CNT_IN_SD 512
		#define I40E_HMC_DIRECT_BP_SIZE 0x200000 /* 2M */
		#define I40E_HMC_PAGED_BP_SIZE 4096
		#define I40E_HMC_PD_BP_BUF_ALIGNMENT 4096
		#define I40E_FIRST_VF_FPM_ID 16

		struct i40e_hmc_obj_info {
		u64 base; /* base addr in FPM */
		u32 max_cnt; /* max count available for this hmc func */
		u32 cnt; /* count of objects driver actually wants to create */
		u64 size; /* size in bytes of one object */
		};

		enum i40e_sd_entry_type {
		I40E_SD_TYPE_INVALID = 0,
		I40E_SD_TYPE_PAGED = 1,
		I40E_SD_TYPE_DIRECT = 2
		};

		struct i40e_hmc_bp {
		enum i40e_sd_entry_type entry_type;
		struct i40e_dma_mem addr; /* populate to be used by hw */
		u32 sd_pd_index;
		u32 ref_cnt;
		};

		struct i40e_hmc_pd_entry {
		struct i40e_hmc_bp bp;
		u32 sd_index;
		bool rsrc_pg;
		bool valid;
		};

		struct i40e_hmc_pd_table {
		struct i40e_dma_mem pd_page_addr; /* populate to be used by hw */
		struct i40e_hmc_pd_entry pd_entry; / [512] for sw book keeping */
		struct i40e_virt_mem pd_entry_virt_mem; /* virt mem for pd_entry */

		u32 ref_cnt;
		u32 sd_index;
		};

		struct i40e_hmc_sd_entry {
		enum i40e_sd_entry_type entry_type;
		bool valid;

		union {
		struct i40e_hmc_pd_table pd_table;
		struct i40e_hmc_bp bp;
		} u;
		};

		struct i40e_hmc_sd_table {
		struct i40e_virt_mem addr; /* used to track sd_entry allocations */
		u32 sd_cnt;
		u32 ref_cnt;
		struct i40e_hmc_sd_entry sd_entry; / (sd_cnt512) entries max /
		};

		struct i40e_hmc_info {
		u32 signature;
		/* equals to pci func num for PF and dynamically allocated for VFs */
		u8 hmc_fn_id;
		u16 first_sd_index; /* index of the first available SD */

		/* hmc objects */
		struct i40e_hmc_obj_info *hmc_obj;
		struct i40e_virt_mem hmc_obj_virt_mem;
		struct i40e_hmc_sd_table sd_table;
		};

		#define I40E_INC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt++)
		#define I40E_INC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt++)
		#define I40E_INC_BP_REFCNT(bp) ((bp)->ref_cnt++)

		#define I40E_DEC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt--)
		#define I40E_DEC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt--)
		#define I40E_DEC_BP_REFCNT(bp) ((bp)->ref_cnt--)

		/**
		* I40E_SET_PF_SD_ENTRY - marks the sd entry as valid in the hardware
		* @hw: pointer to our hw struct
		* @pa: pointer to physical address
		* @sd_index: segment descriptor index
		* @type: if sd entry is direct or paged
		**/
		#define I40E_SET_PF_SD_ENTRY(hw, pa, sd_index, type) \
		{ \
		u32 val1, val2, val3; \
		val1 = (u32)(upper_32_bits(pa)); \
		val2 = (u32)(pa) \| (I40E_HMC_MAX_BP_COUNT << \
		I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) \| \
		((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \
		I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) \| \
		BIT(I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT); \
		val3 = (sd_index) \| BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
		wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
		wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
		wr32((hw), I40E_PFHMC_SDCMD, val3); \
		}

		/**
		* I40E_CLEAR_PF_SD_ENTRY - marks the sd entry as invalid in the hardware
		* @hw: pointer to our hw struct
		* @sd_index: segment descriptor index
		* @type: if sd entry is direct or paged
		**/
		#define I40E_CLEAR_PF_SD_ENTRY(hw, sd_index, type) \
		{ \
		u32 val2, val3; \
		val2 = (I40E_HMC_MAX_BP_COUNT << \
		I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) \| \
		((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \
		I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT); \
		val3 = (sd_index) \| BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
		wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
		wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
		wr32((hw), I40E_PFHMC_SDCMD, val3); \
		}

		/**
		* I40E_INVALIDATE_PF_HMC_PD - Invalidates the pd cache in the hardware
		* @hw: pointer to our hw struct
		* @sd_idx: segment descriptor index
		* @pd_idx: page descriptor index
		**/
		#define I40E_INVALIDATE_PF_HMC_PD(hw, sd_idx, pd_idx) \
		wr32((hw), I40E_PFHMC_PDINV, \
		(((sd_idx) << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) \| \
		((pd_idx) << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)))

		/**
		* I40E_FIND_SD_INDEX_LIMIT - finds segment descriptor index limit
		* @hmc_info: pointer to the HMC configuration information structure
		* @type: type of HMC resources we're searching
		* @index: starting index for the object
		* @cnt: number of objects we're trying to create
		* @sd_idx: pointer to return index of the segment descriptor in question
		* @sd_limit: pointer to return the maximum number of segment descriptors
		*
		* This function calculates the segment descriptor index and index limit
		* for the resource defined by i40e_hmc_rsrc_type.
		**/
		#define I40E_FIND_SD_INDEX_LIMIT(hmc_info, type, index, cnt, sd_idx, sd_limit)\
		{ \
		u64 fpm_addr, fpm_limit; \
		fpm_addr = (hmc_info)->hmc_obj[(type)].base + \
		(hmc_info)->hmc_obj[(type)].size * (index); \
		fpm_limit = fpm_addr + (hmc_info)->hmc_obj[(type)].size * (cnt);\
		*(sd_idx) = (u32)(fpm_addr / I40E_HMC_DIRECT_BP_SIZE); \
		*(sd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_DIRECT_BP_SIZE); \
		/* add one more to the limit to correct our range */ \
		*(sd_limit) += 1; \
		}

		/**
		* I40E_FIND_PD_INDEX_LIMIT - finds page descriptor index limit
		* @hmc_info: pointer to the HMC configuration information struct
		* @type: HMC resource type we're examining
		* @idx: starting index for the object
		* @cnt: number of objects we're trying to create
		* @pd_index: pointer to return page descriptor index
		* @pd_limit: pointer to return page descriptor index limit
		*
		* Calculates the page descriptor index and index limit for the resource
		* defined by i40e_hmc_rsrc_type.
		**/
		#define I40E_FIND_PD_INDEX_LIMIT(hmc_info, type, idx, cnt, pd_index, pd_limit)\
		{ \
		u64 fpm_adr, fpm_limit; \
		fpm_adr = (hmc_info)->hmc_obj[(type)].base + \
		(hmc_info)->hmc_obj[(type)].size * (idx); \
		fpm_limit = fpm_adr + (hmc_info)->hmc_obj[(type)].size * (cnt); \
		*(pd_index) = (u32)(fpm_adr / I40E_HMC_PAGED_BP_SIZE); \
		*(pd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_PAGED_BP_SIZE); \
		/* add one more to the limit to correct our range */ \
		*(pd_limit) += 1; \
		}
		i40e_status i40e_add_sd_table_entry(struct i40e_hw *hw,
		struct i40e_hmc_info *hmc_info,
		u32 sd_index,
		enum i40e_sd_entry_type type,
		u64 direct_mode_sz);

		i40e_status i40e_add_pd_table_entry(struct i40e_hw *hw,
		struct i40e_hmc_info *hmc_info,
		u32 pd_index,
		struct i40e_dma_mem *rsrc_pg);
		i40e_status i40e_remove_pd_bp(struct i40e_hw *hw,
		struct i40e_hmc_info *hmc_info,
		u32 idx);
		i40e_status i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info,
		u32 idx);
		i40e_status i40e_remove_sd_bp_new(struct i40e_hw *hw,
		struct i40e_hmc_info *hmc_info,
		u32 idx, bool is_pf);
		i40e_status i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info,
		u32 idx);
		i40e_status i40e_remove_pd_page_new(struct i40e_hw *hw,
		struct i40e_hmc_info *hmc_info,
		u32 idx, bool is_pf);

		#endif /* _I40E_HMC_H_ */

drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h

deleted100644 → 0

+0 −158

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0 */
		/* Copyright(c) 2013 - 2018 Intel Corporation. */

		#ifndef _I40E_LAN_HMC_H_
		#define _I40E_LAN_HMC_H_

		/* forward-declare the HW struct for the compiler */
		struct i40e_hw;

		/* HMC element context information */

		/* Rx queue context data
		*
		* The sizes of the variables may be larger than needed due to crossing byte
		* boundaries. If we do not have the width of the variable set to the correct
		* size then we could end up shifting bits off the top of the variable when the
		* variable is at the top of a byte and crosses over into the next byte.
		*/
		struct i40e_hmc_obj_rxq {
		u16 head;
		u16 cpuid; /* bigger than needed, see above for reason */
		u64 base;
		u16 qlen;
		#define I40E_RXQ_CTX_DBUFF_SHIFT 7
		u16 dbuff; /* bigger than needed, see above for reason */
		#define I40E_RXQ_CTX_HBUFF_SHIFT 6
		u16 hbuff; /* bigger than needed, see above for reason */
		u8 dtype;
		u8 dsize;
		u8 crcstrip;
		u8 fc_ena;
		u8 l2tsel;
		u8 hsplit_0;
		u8 hsplit_1;
		u8 showiv;
		u32 rxmax; /* bigger than needed, see above for reason */
		u8 tphrdesc_ena;
		u8 tphwdesc_ena;
		u8 tphdata_ena;
		u8 tphhead_ena;
		u16 lrxqthresh; /* bigger than needed, see above for reason */
		u8 prefena; /* NOTE: normally must be set to 1 at init */
		};

		/* Tx queue context data
		*
		* The sizes of the variables may be larger than needed due to crossing byte
		* boundaries. If we do not have the width of the variable set to the correct
		* size then we could end up shifting bits off the top of the variable when the
		* variable is at the top of a byte and crosses over into the next byte.
		*/
		struct i40e_hmc_obj_txq {
		u16 head;
		u8 new_context;
		u64 base;
		u8 fc_ena;
		u8 timesync_ena;
		u8 fd_ena;
		u8 alt_vlan_ena;
		u16 thead_wb;
		u8 cpuid;
		u8 head_wb_ena;
		u16 qlen;
		u8 tphrdesc_ena;
		u8 tphrpacket_ena;
		u8 tphwdesc_ena;
		u64 head_wb_addr;
		u32 crc;
		u16 rdylist;
		u8 rdylist_act;
		};

		/* for hsplit_0 field of Rx HMC context */
		enum i40e_hmc_obj_rx_hsplit_0 {
		I40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT = 0,
		I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 = 1,
		I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP = 2,
		I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,
		I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP = 8,
		};

		/* fcoe_cntx and fcoe_filt are for debugging purpose only */
		struct i40e_hmc_obj_fcoe_cntx {
		u32 rsv[32];
		};

		struct i40e_hmc_obj_fcoe_filt {
		u32 rsv[8];
		};

		/* Context sizes for LAN objects */
		enum i40e_hmc_lan_object_size {
		I40E_HMC_LAN_OBJ_SZ_8 = 0x3,
		I40E_HMC_LAN_OBJ_SZ_16 = 0x4,
		I40E_HMC_LAN_OBJ_SZ_32 = 0x5,
		I40E_HMC_LAN_OBJ_SZ_64 = 0x6,
		I40E_HMC_LAN_OBJ_SZ_128 = 0x7,
		I40E_HMC_LAN_OBJ_SZ_256 = 0x8,
		I40E_HMC_LAN_OBJ_SZ_512 = 0x9,
		};

		#define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512
		#define I40E_HMC_OBJ_SIZE_TXQ 128
		#define I40E_HMC_OBJ_SIZE_RXQ 32
		#define I40E_HMC_OBJ_SIZE_FCOE_CNTX 128
		#define I40E_HMC_OBJ_SIZE_FCOE_FILT 64

		enum i40e_hmc_lan_rsrc_type {
		I40E_HMC_LAN_FULL = 0,
		I40E_HMC_LAN_TX = 1,
		I40E_HMC_LAN_RX = 2,
		I40E_HMC_FCOE_CTX = 3,
		I40E_HMC_FCOE_FILT = 4,
		I40E_HMC_LAN_MAX = 5
		};

		enum i40e_hmc_model {
		I40E_HMC_MODEL_DIRECT_PREFERRED = 0,
		I40E_HMC_MODEL_DIRECT_ONLY = 1,
		I40E_HMC_MODEL_PAGED_ONLY = 2,
		I40E_HMC_MODEL_UNKNOWN,
		};

		struct i40e_hmc_lan_create_obj_info {
		struct i40e_hmc_info *hmc_info;
		u32 rsrc_type;
		u32 start_idx;
		u32 count;
		enum i40e_sd_entry_type entry_type;
		u64 direct_mode_sz;
		};

		struct i40e_hmc_lan_delete_obj_info {
		struct i40e_hmc_info *hmc_info;
		u32 rsrc_type;
		u32 start_idx;
		u32 count;
		};

		i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
		u32 rxq_num, u32 fcoe_cntx_num,
		u32 fcoe_filt_num);
		i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw,
		enum i40e_hmc_model model);
		i40e_status i40e_shutdown_lan_hmc(struct i40e_hw *hw);

		i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
		u16 queue);
		i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
		u16 queue,
		struct i40e_hmc_obj_txq *s);
		i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
		u16 queue);
		i40e_status i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
		u16 queue,
		struct i40e_hmc_obj_rxq *s);

		#endif /* _I40E_LAN_HMC_H_ */

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