Commit ee4adbbc authored by Taniya Das's avatar Taniya Das Committed by Stephen Boyd
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clk: qcom: clk-alpha-pll: Refactor trion PLL



Remove duplicate function for calculating the round rate of PLL and also
update the trion pll ops to use the common function.

Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
Signed-off-by: default avatarVenkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20200224045003.3783838-3-vkoul@kernel.org


Reviewed-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 57d98e8e
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+6 −27
Original line number Diff line number Diff line
@@ -845,33 +845,12 @@ static unsigned long
clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
	struct regmap *regmap = pll->clkr.regmap;
	u32 l, frac;
	u64 prate = parent_rate;

	regmap_read(regmap, PLL_L_VAL(pll), &l);
	regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);

	return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
}

static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
				     unsigned long *prate)
{
	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
	unsigned long min_freq, max_freq;
	u32 l;
	u64 a;

	rate = alpha_pll_round_rate(rate, *prate,
				    &l, &a, ALPHA_REG_16BIT_WIDTH);
	if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
		return rate;
	u32 l, frac, alpha_width = pll_alpha_width(pll);

	min_freq = pll->vco_table[0].min_freq;
	max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
	regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
	regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);

	return clamp(rate, min_freq, max_freq);
	return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
}

const struct clk_ops clk_alpha_pll_fixed_ops = {
@@ -917,7 +896,7 @@ const struct clk_ops clk_trion_fixed_pll_ops = {
	.disable = clk_trion_pll_disable,
	.is_enabled = clk_trion_pll_is_enabled,
	.recalc_rate = clk_trion_pll_recalc_rate,
	.round_rate = clk_trion_pll_round_rate,
	.round_rate = clk_alpha_pll_round_rate,
};
EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);

@@ -1173,7 +1152,7 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
	 * Due to limited number of bits for fractional rate programming, the
	 * rounded up rate could be marginally higher than the requested rate.
	 */
	if (rrate > max || rrate < rate) {
	if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
		pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
		       clk_hw_get_name(hw), rrate, rate, max);
		return -EINVAL;