Merge tag 'zynq-soc-for-3.20' of https://github.com/Xilinx/linux-xlnx into next/soc (ee481c84) · Commits · 戴 / test

arch/arm/Kconfig

+1 −1

Original line number	Diff line number	Diff line
		@@ -1490,7 +1490,7 @@ config ARM_PSCI
		# selected platforms.
		config ARCH_NR_GPIO
		int
		default 1024 if ARCH_SHMOBILE \|\| ARCH_TEGRA
		default 1024 if ARCH_SHMOBILE \|\| ARCH_TEGRA \|\| ARCH_ZYNQ
		default 512 if ARCH_EXYNOS \|\| ARCH_KEYSTONE \|\| SOC_OMAP5 \|\| \
		SOC_DRA7XX \|\| ARCH_S3C24XX \|\| ARCH_S3C64XX \|\| ARCH_S5PV210
		default 416 if ARCH_SUNXI

+2 −0

Original line number	Diff line number	Diff line
		@@ -9,6 +9,8 @@ config ARCH_ZYNQ
		select HAVE_ARM_TWD if SMP
		select ICST
		select MFD_SYSCON
		select PINCTRL
		select PINCTRL_ZYNQ
		select SOC_BUS
		help
		Support for Xilinx Zynq ARM Cortex A9 Platform

+0 −2

Original line number	Diff line number	Diff line
		@@ -146,8 +146,6 @@ out:

		platform_device_register(&zynq_cpuidle_device);
		platform_device_register_full(&devinfo);

		zynq_slcr_init();
		}

		static void __init zynq_timer_init(void)

+1 −1

Original line number	Diff line number	Diff line
		@@ -61,7 +61,7 @@ static void __iomem zynq_pm_ioremap(const char comp)
		/**
		* zynq_pm_late_init() - Power management init
		*
		* Initialization of power management related featurs and infrastructure.
		* Initialization of power management related features and infrastructure.
		*/
		void __init zynq_pm_late_init(void)
		{

+7 −28

Original line number	Diff line number	Diff line
		@@ -47,11 +47,6 @@ static struct regmap *zynq_slcr_regmap;
		*/
		static int zynq_slcr_write(u32 val, u32 offset)
		{
		if (!zynq_slcr_regmap) {
		writel(val, zynq_slcr_base + offset);
		return 0;
		}

		return regmap_write(zynq_slcr_regmap, offset, val);
		}

		@@ -65,12 +60,7 @@ static int zynq_slcr_write(u32 val, u32 offset)
		*/
		static int zynq_slcr_read(u32 *val, u32 offset)
		{
		if (zynq_slcr_regmap)
		return regmap_read(zynq_slcr_regmap, offset, val);

		*val = readl(zynq_slcr_base + offset);

		return 0;
		}

		/**
		@@ -195,23 +185,6 @@ void zynq_slcr_cpu_state_write(int cpu, bool die)
		writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
		}

		/**
		* zynq_slcr_init - Regular slcr driver init
		* Return: 0 on success, negative errno otherwise.
		*
		* Called early during boot from platform code to remap SLCR area.
		*/
		int __init zynq_slcr_init(void)
		{
		zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
		if (IS_ERR(zynq_slcr_regmap)) {
		pr_err("%s: failed to find zynq-slcr\n", __func__);
		return -ENODEV;
		}

		return 0;
		}

		/**
		* zynq_early_slcr_init - Early slcr init function
		*
		@@ -237,6 +210,12 @@ int __init zynq_early_slcr_init(void)

		np->data = (__force void *)zynq_slcr_base;

		zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
		if (IS_ERR(zynq_slcr_regmap)) {
		pr_err("%s: failed to find zynq-slcr\n", __func__);
		return -ENODEV;
		}

		/* unlock the SLCR so that registers can be changed */
		zynq_slcr_unlock();