Commit ee440336 authored by Stefan Agner's avatar Stefan Agner Committed by Russell King
Browse files

ARM: 8990/1: use VFP assembler mnemonics in register load/store macros 

The integrated assembler of Clang 10 and earlier do not allow to access
the VFP registers through the coprocessor load/store instructions:
<instantiation>:4:6: error: invalid operand for instruction
 LDC p11, cr0, [r10],#32*4 @ FLDMIAD r10!, {d0-d15}
     ^

This has been addressed with Clang 11 [0]. However, to support earlier
versions of Clang and for better readability use of VFP assembler
mnemonics still is preferred.

Replace the coprocessor load/store instructions with explicit assembler
mnemonics to accessing the floating point coprocessor registers. Use
assembler directives to select the appropriate FPU version.

This allows to build these macros with GNU assembler as well as with
Clang's built-in assembler.

[0] https://reviews.llvm.org/D59733

Link: https://github.com/ClangBuiltLinux/linux/issues/905



Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parent a6c30873

arch/arm/include/asm/vfpmacros.h

+11 −8
Original line number Diff line number Diff line
@@ -19,23 +19,25 @@ 


	@ read all the working registers back into the VFP

	.macro	VFPFLDMIA, base, tmp

	.fpu	vfpv2

#if __LINUX_ARM_ARCH__ < 6

	LDC	p11, cr0, [\base],#33*4		    @ FLDMIAX \base!, {d0-d15}

	fldmiax	\base!, {d0-d15}

#else

	LDC	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d0-d15}

	vldmia	\base!, {d0-d15}

#endif

#ifdef CONFIG_VFPv3

	.fpu	vfpv3

#if __LINUX_ARM_ARCH__ <= 6

	ldr	\tmp, =elf_hwcap		    @ may not have MVFR regs

	ldr	\tmp, [\tmp, #0]

	tst	\tmp, #HWCAP_VFPD32

	ldclne	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}

	vldmiane \base!, {d16-d31}

	addeq	\base, \base, #32*4		    @ step over unused register space

#else

	VFPFMRX	\tmp, MVFR0			    @ Media and VFP Feature Register 0

	and	\tmp, \tmp, #MVFR0_A_SIMD_MASK	    @ A_SIMD field

	cmp	\tmp, #2			    @ 32 x 64bit registers?

	ldcleq	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}

	vldmiaeq \base!, {d16-d31}

	addne	\base, \base, #32*4		    @ step over unused register space

#endif

#endif
@@ -44,22 +46,23 @@ 
	@ write all the working registers out of the VFP

	.macro	VFPFSTMIA, base, tmp

#if __LINUX_ARM_ARCH__ < 6

	STC	p11, cr0, [\base],#33*4		    @ FSTMIAX \base!, {d0-d15}

	fstmiax	\base!, {d0-d15}

#else

	STC	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d0-d15}

	vstmia	\base!, {d0-d15}

#endif

#ifdef CONFIG_VFPv3

	.fpu	vfpv3

#if __LINUX_ARM_ARCH__ <= 6

	ldr	\tmp, =elf_hwcap		    @ may not have MVFR regs

	ldr	\tmp, [\tmp, #0]

	tst	\tmp, #HWCAP_VFPD32

	stclne	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}

	vstmiane \base!, {d16-d31}

	addeq	\base, \base, #32*4		    @ step over unused register space

#else

	VFPFMRX	\tmp, MVFR0			    @ Media and VFP Feature Register 0

	and	\tmp, \tmp, #MVFR0_A_SIMD_MASK	    @ A_SIMD field

	cmp	\tmp, #2			    @ 32 x 64bit registers?

	stcleq	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}

	vstmiaeq \base!, {d16-d31}

	addne	\base, \base, #32*4		    @ step over unused register space

#endif

#endif

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