Commit ee249cbe authored by Shawn Guo's avatar Shawn Guo Committed by Michael Turquette
Browse files

clk: zte: pd_bit is not 0 on zx296718 



The bit 0 of PLL_CFG0 register is not powerdown on zx296718, but part of
of postdiv2 field.  The consequence is that functions like hw_to_idx()
and zx_pll_enable() will end up tampering the postdiv2 of the PLL.

Let's fix it by defining pd_bit 0xff which is obviously invalid for a
bit position and having PLL driver check the validity before operating
on the bit.

Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Reviewed-by: default avatarJun Nie <jun.nie@linaro.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
parent 5790d801

drivers/clk/zte/clk.c

+11 −1
Original line number Diff line number Diff line
@@ -52,6 +52,9 @@ static int hw_to_idx(struct clk_zx_pll *zx_pll) 


	/* For matching the value in lookup table */

	hw_cfg0 &= ~BIT(zx_pll->lock_bit);



	/* Check availability of pd_bit */

	if (zx_pll->pd_bit < 32)

		hw_cfg0 |= BIT(zx_pll->pd_bit);



	for (i = 0; i < zx_pll->count; i++) {
@@ -108,6 +111,10 @@ static int zx_pll_enable(struct clk_hw *hw) 
	struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);

	u32 reg;



	/* If pd_bit is not available, simply return success. */

	if (zx_pll->pd_bit > 31)

		return 0;



	reg = readl_relaxed(zx_pll->reg_base);

	writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base);
@@ -120,6 +127,9 @@ static void zx_pll_disable(struct clk_hw *hw) 
	struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);

	u32 reg;



	if (zx_pll->pd_bit > 31)

		return;



	reg = readl_relaxed(zx_pll->reg_base);

	writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base);

}

drivers/clk/zte/clk.h

+5 −1
Original line number Diff line number Diff line
@@ -66,8 +66,12 @@ struct clk_zx_pll { 
				CLK_GET_RATE_NOCACHE),			\

}



/*

 * The pd_bit is not available on ZX296718, so let's pass something

 * bigger than 31, e.g. 0xff, to indicate that.

 */

#define ZX296718_PLL(_name, _parent, _reg, _table)			\

ZX_PLL(_name, _parent, _reg, _table, 0, 30)

ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)



struct zx_clk_gate {

	struct clk_gate gate;

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