Commit ee139385 authored Sep 25, 2020 by Kan Liang Committed by Peter Zijlstra Sep 29, 2020

perf/x86/intel/uncore: Reduce the number of CBOX counters



An oops is triggered by the fuzzy test.

[  327.853081] unchecked MSR access error: RDMSR from 0x70c at rIP:
0xffffffffc082c820 (uncore_msr_read_counter+0x10/0x50 [intel_uncore])
[  327.853083] Call Trace:
[  327.853085]  <IRQ>
[  327.853089]  uncore_pmu_event_start+0x85/0x170 [intel_uncore]
[  327.853093]  uncore_pmu_event_add+0x1a4/0x410 [intel_uncore]
[  327.853097]  ? event_sched_in.isra.118+0xca/0x240

There are 2 GP counters for each CBOX, but the current code claims 4
counters. Accessing the invalid registers triggers the oops.

Fixes: 6e394376 ("perf/x86/intel/uncore: Add Intel Icelake uncore support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200925134905.8839-3-kan.liang@linux.intel.com

parent 8f5d41f3

arch/x86/events/intel/uncore_snb.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -325,7 +325,7 @@ static struct intel_uncore_ops icl_uncore_msr_ops = {

		static struct intel_uncore_type icl_uncore_cbox = {
		.name = "cbox",
		.num_counters = 4,
		.num_counters = 2,
		.perf_ctr_bits = 44,
		.perf_ctr = ICL_UNC_CBO_0_PER_CTR0,
		.event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0,

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