dt-bindings: net: dwmac-meson: Document the "timing-adjustment" clock (ee0b8e6d) · Commits · 戴 / test

The PRG_ETHERNET registers can add an RX delay in RGMII mode. This requires an internal re-timing circuit whose input clock is called "timing adjustment clock". Document this clock input so the clock can be enabled as needed. Reviewed-by:

Andrew Lunn <andrew@lunn.ch> Signed-off-by:

Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:

David S. Miller <davem@davemloft.net>

Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml

+7 −3

Original line number	Diff line number	Diff line
		@@ -40,18 +40,22 @@ allOf:
		then:
		properties:
		clocks:
		minItems: 3
		maxItems: 4
		items:
		- description: GMAC main clock
		- description: First parent clock of the internal mux
		- description: Second parent clock of the internal mux
		- description: The clock which drives the timing adjustment logic

		clock-names:
		minItems: 3
		maxItems: 3
		maxItems: 4
		items:
		- const: stmmaceth
		- const: clkin0
		- const: clkin1
		- const: timing-adjustment

		amlogic,tx-delay-ns:
		$ref: /schemas/types.yaml#definitions/uint32
		@@ -120,7 +124,7 @@ examples:
		reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
		interrupts = <8>;
		interrupt-names = "macirq";
		clocks = <&clk_eth>, <&clkc_fclk_div2>, <&clk_mpll2>;
		clock-names = "stmmaceth", "clkin0", "clkin1";
		clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;
		clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
		phy-mode = "rgmii";
		};

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