Commit edf413f6 authored by Axel Lin's avatar Axel Lin Committed by Mark Brown
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ASoC: sta32x: Write the register default value to cache for reserved registers 



Chip documentation explicitly requires that the reset values
of reserved register bits are left untouched.

codec->hw_read is broken now.
Here we use below trick to avoid writing to reserved registers while resume.
Write the register default value to cache for reserved registers,
so the write to the these registers are suppressed by the cache
restore code when it skips writes of default registers.

Signed-off-by: default avatarAxel Lin <axel.lin@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent f0bbc2b5

sound/soc/codecs/sta32x.c

+13 −15
Original line number Diff line number Diff line
@@ -756,21 +756,19 @@ static int sta32x_probe(struct snd_soc_codec *codec) 
		return ret;

	}



	/* preserve reset values of reserved register bits */

	snd_soc_cache_write(codec, STA32X_CONFC,

			    codec->hw_read(codec, STA32X_CONFC));

	snd_soc_cache_write(codec, STA32X_CONFE,

			    codec->hw_read(codec, STA32X_CONFE));

	snd_soc_cache_write(codec, STA32X_CONFF,

			    codec->hw_read(codec, STA32X_CONFF));

	snd_soc_cache_write(codec, STA32X_MMUTE,

			    codec->hw_read(codec, STA32X_MMUTE));

	snd_soc_cache_write(codec, STA32X_AUTO1,

			    codec->hw_read(codec, STA32X_AUTO1));

	snd_soc_cache_write(codec, STA32X_AUTO3,

			    codec->hw_read(codec, STA32X_AUTO3));

	snd_soc_cache_write(codec, STA32X_C3CFG,

			    codec->hw_read(codec, STA32X_C3CFG));

	/* Chip documentation explicitly requires that the reset values

	 * of reserved register bits are left untouched.

	 * Write the register default value to cache for reserved registers,

	 * so the write to the these registers are suppressed by the cache

	 * restore code when it skips writes of default registers.

	 */

	snd_soc_cache_write(codec, STA32X_CONFC, 0xc2);

	snd_soc_cache_write(codec, STA32X_CONFE, 0xc2);

	snd_soc_cache_write(codec, STA32X_CONFF, 0x5c);

	snd_soc_cache_write(codec, STA32X_MMUTE, 0x10);

	snd_soc_cache_write(codec, STA32X_AUTO1, 0x60);

	snd_soc_cache_write(codec, STA32X_AUTO3, 0x00);

	snd_soc_cache_write(codec, STA32X_C3CFG, 0x40);



	/* FIXME enable thermal warning adjustment and recovery  */

	snd_soc_update_bits(codec, STA32X_CONFA,

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