iwlwifi: pcie: add context information support (eda50cde) · Commits · 戴 / test

drivers/net/wireless/intel/iwlwifi/Makefile

+1 −0

Original line number	Diff line number	Diff line
		@@ -7,6 +7,7 @@ iwlwifi-objs += iwl-notif-wait.o
		iwlwifi-objs += iwl-eeprom-read.o iwl-eeprom-parse.o
		iwlwifi-objs += iwl-phy-db.o iwl-nvm-parse.o
		iwlwifi-objs += pcie/drv.o pcie/rx.o pcie/tx.o pcie/trans.o
		iwlwifi-objs += pcie/ctxt-info.o pcie/trans-gen2.o
		iwlwifi-$(CONFIG_IWLDVM) += iwl-1000.o iwl-2000.o iwl-5000.o iwl-6000.o
		iwlwifi-$(CONFIG_IWLMVM) += iwl-7000.o iwl-8000.o iwl-9000.o iwl-a000.o
		iwlwifi-objs += iwl-trans.o

drivers/net/wireless/intel/iwlwifi/iwl-context-info.h

0 → 100644

+203 −0

Original line number	Diff line number	Diff line
		/******************************************************************************
		*
		* This file is provided under a dual BSD/GPLv2 license. When using or
		* redistributing this file, you may do so under either license.
		*
		* GPL LICENSE SUMMARY
		*
		* Copyright(c) 2017 Intel Deutschland GmbH
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of version 2 of the GNU General Public License as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful, but
		* WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
		* General Public License for more details.
		*
		* BSD LICENSE
		*
		* Copyright(c) 2017 Intel Deutschland GmbH
		* All rights reserved.
		*
		* Redistribution and use in source and binary forms, with or without
		* modification, are permitted provided that the following conditions
		* are met:
		*
		* * Redistributions of source code must retain the above copyright
		* notice, this list of conditions and the following disclaimer.
		* * Redistributions in binary form must reproduce the above copyright
		* notice, this list of conditions and the following disclaimer in
		* the documentation and/or other materials provided with the
		* distribution.
		* * Neither the name Intel Corporation nor the names of its
		* contributors may be used to endorse or promote products derived
		* from this software without specific prior written permission.
		*
		* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
		* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
		* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
		* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
		* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
		* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
		* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
		* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
		* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
		* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		*
		*****************************************************************************/

		#ifndef __iwl_context_info_file_h__
		#define __iwl_context_info_file_h__

		/* maximmum number of DRAM map entries supported by FW */
		#define IWL_MAX_DRAM_ENTRY 64
		#define CSR_CTXT_INFO_BA 0x40

		/**
		* enum iwl_context_info_flags - Context information control flags
		* @IWL_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting
		* the init done for driver command that configures several system modes
		* @IWL_CTXT_INFO_EARLY_DEBUG: enable early debug
		* @IWL_CTXT_INFO_ENABLE_CDMP: enable core dump
		* @IWL_CTXT_INFO_RB_SIZE_4K: Use 4K RB size (the default is 2K)
		* @IWL_CTXT_INFO_RB_CB_SIZE_POS: position of the RBD Cyclic Buffer Size
		* exponent, the actual size is 2**value, valid sizes are 8-2048.
		* The value is four bits long. Maximum valid exponent is 12
		* @IWL_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the
		* default is short format - not supported by the driver)
		*/
		enum iwl_context_info_flags {
		IWL_CTXT_INFO_AUTO_FUNC_INIT = BIT(0),
		IWL_CTXT_INFO_EARLY_DEBUG = BIT(1),
		IWL_CTXT_INFO_ENABLE_CDMP = BIT(2),
		IWL_CTXT_INFO_RB_SIZE_4K = BIT(3),
		IWL_CTXT_INFO_RB_CB_SIZE_POS = 4,
		IWL_CTXT_INFO_TFD_FORMAT_LONG = BIT(8),
		};

		/*
		* struct iwl_context_info_version - version structure
		* @mac_id: SKU and revision id
		* @version: context information version id
		* @size: the size of the context information in DWs
		*/
		struct iwl_context_info_version {
		__le16 mac_id;
		__le16 version;
		__le16 size;
		__le16 reserved;
		} __packed;

		/*
		* struct iwl_context_info_control - version structure
		* @control_flags: context information flags see &enum iwl_context_info_flags
		*/
		struct iwl_context_info_control {
		__le32 control_flags;
		__le32 reserved;
		} __packed;

		/*
		* struct iwl_context_info_dram - images DRAM map
		* each entry in the map represents a DRAM chunk of up to 32 KB
		* @umac_img: UMAC image DRAM map
		* @lmac_img: LMAC image DRAM map
		* @virtual_img: paged image DRAM map
		*/
		struct iwl_context_info_dram {
		__le64 umac_img[IWL_MAX_DRAM_ENTRY];
		__le64 lmac_img[IWL_MAX_DRAM_ENTRY];
		__le64 virtual_img[IWL_MAX_DRAM_ENTRY];
		} __packed;

		/*
		* struct iwl_context_info_rbd_cfg - RBDs configuration
		* @free_rbd_addr: default queue free RB CB base address
		* @used_rbd_addr: default queue used RB CB base address
		* @status_wr_ptr: default queue used RB status write pointer
		*/
		struct iwl_context_info_rbd_cfg {
		__le64 free_rbd_addr;
		__le64 used_rbd_addr;
		__le64 status_wr_ptr;
		} __packed;

		/*
		* struct iwl_context_info_hcmd_cfg - command queue configuration
		* @cmd_queue_addr: address of command queue
		* @cmd_queue_size: number of entries
		*/
		struct iwl_context_info_hcmd_cfg {
		__le64 cmd_queue_addr;
		u8 cmd_queue_size;
		u8 reserved[7];
		} __packed;

		/*
		* struct iwl_context_info_dump_cfg - Core Dump configuration
		* @core_dump_addr: core dump (debug DRAM address) start address
		* @core_dump_size: size, in DWs
		*/
		struct iwl_context_info_dump_cfg {
		__le64 core_dump_addr;
		__le32 core_dump_size;
		__le32 reserved;
		} __packed;

		/*
		* struct iwl_context_info_pnvm_cfg - platform NVM data configuration
		* @platform_nvm_addr: Platform NVM data start address
		* @platform_nvm_size: size in DWs
		*/
		struct iwl_context_info_pnvm_cfg {
		__le64 platform_nvm_addr;
		__le32 platform_nvm_size;
		__le32 reserved;
		} __packed;

		/*
		* struct iwl_context_info_early_dbg_cfg - early debug configuration for
		* dumping DRAM addresses
		* @early_debug_addr: early debug start address
		* @early_debug_size: size in DWs
		*/
		struct iwl_context_info_early_dbg_cfg {
		__le64 early_debug_addr;
		__le32 early_debug_size;
		__le32 reserved;
		} __packed;

		/*
		* struct iwl_context_info - device INIT configuration
		* @version: version information of context info and HW
		* @control: control flags of FH configurations
		* @rbd_cfg: default RX queue configuration
		* @hcmd_cfg: command queue configuration
		* @dump_cfg: core dump data
		* @edbg_cfg: early debug configuration
		* @pnvm_cfg: platform nvm configuration
		* @dram: firmware image addresses in DRAM
		*/
		struct iwl_context_info {
		struct iwl_context_info_version version;
		struct iwl_context_info_control control;
		__le64 reserved0;
		struct iwl_context_info_rbd_cfg rbd_cfg;
		struct iwl_context_info_hcmd_cfg hcmd_cfg;
		__le32 reserved1[4];
		struct iwl_context_info_dump_cfg dump_cfg;
		struct iwl_context_info_early_dbg_cfg edbg_cfg;
		struct iwl_context_info_pnvm_cfg pnvm_cfg;
		__le32 reserved2[16];
		struct iwl_context_info_dram dram;
		__le32 reserved3[16];
		} __packed;

		int iwl_pcie_ctxt_info_init(struct iwl_trans trans, const struct fw_img fw);
		void iwl_pcie_ctxt_info_free(struct iwl_trans *trans);
		void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans);

		#endif /* __iwl_context_info_file_h__ */

drivers/net/wireless/intel/iwlwifi/iwl-fh.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -614,6 +614,8 @@ static inline unsigned int FH_MEM_CBBC_QUEUE(struct iwl_trans *trans,
		#define RX_POOL_SIZE (MQ_RX_NUM_RBDS + \
		IWL_MAX_RX_HW_QUEUES * \
		(RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC))
		/* cb size is the exponent */
		#define RX_QUEUE_CB_SIZE(x) ilog2(x)

		#define RX_QUEUE_SIZE 256
		#define RX_QUEUE_MASK 255
		@@ -639,6 +641,8 @@ struct iwl_rb_status {


		#define TFD_QUEUE_SIZE_MAX (256)
		/* cb size is the exponent - 3 */
		#define TFD_QUEUE_CB_SIZE(x) (ilog2(x) - 3)
		#define TFD_QUEUE_SIZE_BC_DUP (64)
		#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
		#define IWL_TX_DMA_MASK DMA_BIT_MASK(36)

drivers/net/wireless/intel/iwlwifi/iwl-prph.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -309,6 +309,7 @@
		* Note this address is cleared after MAC reset.
		*/
		#define UREG_UCODE_LOAD_STATUS (0xa05c40)
		#define UREG_CPU_INIT_RUN (0xa05c44)

		#define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR (0x1E78)
		#define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR (0x1E7C)

drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c

0 → 100644

+274 −0

Original line number	Diff line number	Diff line
		/******************************************************************************
		*
		* This file is provided under a dual BSD/GPLv2 license. When using or
		* redistributing this file, you may do so under either license.
		*
		* GPL LICENSE SUMMARY
		*
		* Copyright(c) 2017 Intel Deutschland GmbH
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of version 2 of the GNU General Public License as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful, but
		* WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
		* General Public License for more details.
		*
		* BSD LICENSE
		*
		* Copyright(c) 2017 Intel Deutschland GmbH
		* All rights reserved.
		*
		* Redistribution and use in source and binary forms, with or without
		* modification, are permitted provided that the following conditions
		* are met:
		*
		* * Redistributions of source code must retain the above copyright
		* notice, this list of conditions and the following disclaimer.
		* * Redistributions in binary form must reproduce the above copyright
		* notice, this list of conditions and the following disclaimer in
		* the documentation and/or other materials provided with the
		* distribution.
		* * Neither the name Intel Corporation nor the names of its
		* contributors may be used to endorse or promote products derived
		* from this software without specific prior written permission.
		*
		* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
		* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
		* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
		* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
		* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
		* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
		* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
		* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
		* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
		* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
		* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		*
		*****************************************************************************/

		#include "iwl-trans.h"
		#include "iwl-fh.h"
		#include "iwl-context-info.h"
		#include "internal.h"
		#include "iwl-prph.h"

		static int iwl_pcie_get_num_sections(const struct fw_img *fw,
		int start)
		{
		int i = 0;

		while (start < fw->num_sec &&
		fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION &&
		fw->sec[start].offset != PAGING_SEPARATOR_SECTION) {
		start++;
		i++;
		}

		return i;
		}

		static int iwl_pcie_ctxt_info_alloc_dma(struct iwl_trans *trans,
		const struct fw_desc *sec,
		struct iwl_dram_data *dram)
		{
		dram->block = dma_alloc_coherent(trans->dev, sec->len,
		&dram->physical,
		GFP_KERNEL);
		if (!dram->block)
		return -ENOMEM;

		dram->size = sec->len;
		memcpy(dram->block, sec->data, sec->len);

		return 0;
		}

		static void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans)
		{
		struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
		struct iwl_self_init_dram *dram = &trans_pcie->init_dram;
		int i;

		if (!dram->fw) {
		WARN_ON(dram->fw_cnt);
		return;
		}

		for (i = 0; i < dram->fw_cnt; i++)
		dma_free_coherent(trans->dev, dram->fw[i].size,
		dram->fw[i].block, dram->fw[i].physical);

		kfree(dram->fw);
		dram->fw_cnt = 0;
		}

		void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans)
		{
		struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
		struct iwl_self_init_dram *dram = &trans_pcie->init_dram;
		int i;

		if (!dram->paging) {
		WARN_ON(dram->paging_cnt);
		return;
		}

		/* free paging*/
		for (i = 0; i < dram->paging_cnt; i++)
		dma_free_coherent(trans->dev, dram->paging[i].size,
		dram->paging[i].block,
		dram->paging[i].physical);

		kfree(dram->paging);
		dram->paging_cnt = 0;
		}

		static int iwl_pcie_ctxt_info_init_fw_sec(struct iwl_trans *trans,
		const struct fw_img *fw,
		struct iwl_context_info *ctxt_info)
		{
		struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
		struct iwl_self_init_dram *dram = &trans_pcie->init_dram;
		struct iwl_context_info_dram *ctxt_dram = &ctxt_info->dram;
		int i, ret, lmac_cnt, umac_cnt, paging_cnt;

		lmac_cnt = iwl_pcie_get_num_sections(fw, 0);
		/* add 1 due to separator */
		umac_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + 1);
		/* add 2 due to separators */
		paging_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + umac_cnt + 2);

		dram->fw = kcalloc(umac_cnt + lmac_cnt, sizeof(*dram->fw), GFP_KERNEL);
		if (!dram->fw)
		return -ENOMEM;
		dram->paging = kcalloc(paging_cnt, sizeof(*dram->paging), GFP_KERNEL);
		if (!dram->paging)
		return -ENOMEM;

		/* initialize lmac sections */
		for (i = 0; i < lmac_cnt; i++) {
		ret = iwl_pcie_ctxt_info_alloc_dma(trans, &fw->sec[i],
		&dram->fw[dram->fw_cnt]);
		if (ret)
		return ret;
		ctxt_dram->lmac_img[i] =
		cpu_to_le64(dram->fw[dram->fw_cnt].physical);
		dram->fw_cnt++;
		}

		/* initialize umac sections */
		for (i = 0; i < umac_cnt; i++) {
		/* access FW with +1 to make up for lmac separator */
		ret = iwl_pcie_ctxt_info_alloc_dma(trans,
		&fw->sec[dram->fw_cnt + 1],
		&dram->fw[dram->fw_cnt]);
		if (ret)
		return ret;
		ctxt_dram->umac_img[i] =
		cpu_to_le64(dram->fw[dram->fw_cnt].physical);
		dram->fw_cnt++;
		}

		/*
		* Initialize paging.
		* Paging memory isn't stored in dram->fw as the umac and lmac - it is
		* stored separately.
		* This is since the timing of its release is different -
		* while fw memory can be released on alive, the paging memory can be
		* freed only when the device goes down.
		* Given that, the logic here in accessing the fw image is a bit
		* different - fw_cnt isn't changing so loop counter is added to it.
		*/
		for (i = 0; i < paging_cnt; i++) {
		/* access FW with +2 to make up for lmac & umac separators */
		int fw_idx = dram->fw_cnt + i + 2;

		ret = iwl_pcie_ctxt_info_alloc_dma(trans, &fw->sec[fw_idx],
		&dram->paging[i]);
		if (ret)
		return ret;

		ctxt_dram->virtual_img[i] =
		cpu_to_le64(dram->paging[i].physical);
		dram->paging_cnt++;
		}

		return 0;
		}

		int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
		const struct fw_img *fw)
		{
		struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
		struct iwl_context_info *ctxt_info;
		struct iwl_context_info_rbd_cfg *rx_cfg;
		u32 control_flags = 0;
		int ret;

		ctxt_info = dma_alloc_coherent(trans->dev, sizeof(*ctxt_info),
		&trans_pcie->ctxt_info_dma_addr,
		GFP_KERNEL);
		if (!ctxt_info)
		return -ENOMEM;

		ctxt_info->version.version = 0;
		ctxt_info->version.mac_id =
		cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
		/* size is in DWs */
		ctxt_info->version.size = cpu_to_le16(sizeof(*ctxt_info) / 4);

		BUILD_BUG_ON(RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE) > 0xF);
		control_flags = IWL_CTXT_INFO_RB_SIZE_4K \|
		IWL_CTXT_INFO_TFD_FORMAT_LONG \|
		RX_QUEUE_CB_SIZE(MQ_RX_TABLE_SIZE) <<
		IWL_CTXT_INFO_RB_CB_SIZE_POS;
		ctxt_info->control.control_flags = cpu_to_le32(control_flags);

		/* initialize RX default queue */
		rx_cfg = &ctxt_info->rbd_cfg;
		rx_cfg->free_rbd_addr = cpu_to_le64(trans_pcie->rxq->bd_dma);
		rx_cfg->used_rbd_addr = cpu_to_le64(trans_pcie->rxq->used_bd_dma);
		rx_cfg->status_wr_ptr = cpu_to_le64(trans_pcie->rxq->rb_stts_dma);

		/* initialize TX command queue */
		ctxt_info->hcmd_cfg.cmd_queue_addr =
		cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue].dma_addr);
		ctxt_info->hcmd_cfg.cmd_queue_size =
		TFD_QUEUE_CB_SIZE(TFD_QUEUE_SIZE_MAX);

		/* allocate ucode sections in dram and set addresses */
		ret = iwl_pcie_ctxt_info_init_fw_sec(trans, fw, ctxt_info);
		if (ret)
		return ret;

		trans_pcie->ctxt_info = ctxt_info;

		iwl_enable_interrupts(trans);

		/* kick FW self load */
		iwl_write64(trans, CSR_CTXT_INFO_BA, trans_pcie->ctxt_info_dma_addr);
		iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);

		/* Context info will be released upon alive or failure to get one */

		return 0;
		}

		void iwl_pcie_ctxt_info_free(struct iwl_trans *trans)
		{
		struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);

		if (!trans_pcie->ctxt_info)
		return;

		dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
		trans_pcie->ctxt_info,
		trans_pcie->ctxt_info_dma_addr);
		trans_pcie->ctxt_info_dma_addr = 0;
		trans_pcie->ctxt_info = NULL;

		iwl_pcie_ctxt_info_free_fw_img(trans);
		}

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