Commit ed9891bf authored by Stefan Agner's avatar Stefan Agner Committed by Greg Kroah-Hartman
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serial: fsl_lpuart: calculate DMA burst 



The DMA burst size must match the transmit FIFO depth in order
to make sure all character are transmitted. This patch calculates
DMA burst size by using FIFO depth rather than use the hardcoded
16 bytes. This is required since some UARTs (e.g. UART2 on Vybrid)
have a FIFO depth of 8 bytes.

Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 90abef91

drivers/tty/serial/fsl_lpuart.c

+13 −14
Original line number Diff line number Diff line
@@ -117,8 +117,6 @@ 
#define UARTSFIFO_TXOF		0x02

#define UARTSFIFO_RXUF		0x01



#define DMA_MAXBURST		16

#define DMA_MAXBURST_MASK	(DMA_MAXBURST - 1)

#define FSL_UART_RX_DMA_BUFFER_SIZE	64



#define DRIVER_NAME	"fsl-lpuart"
@@ -236,7 +234,7 @@ static int lpuart_dma_tx(struct lpuart_port *sport, unsigned long count) 


	dma_sync_single_for_device(sport->port.dev, sport->dma_tx_buf_bus,

				UART_XMIT_SIZE, DMA_TO_DEVICE);

	sport->dma_tx_bytes = count & ~(DMA_MAXBURST_MASK);

	sport->dma_tx_bytes = count & ~(sport->txfifo_size - 1);

	tx_bus_addr = sport->dma_tx_buf_bus + xmit->tail;

	sport->dma_tx_desc = dmaengine_prep_slave_single(sport->dma_tx_chan,

					tx_bus_addr, sport->dma_tx_bytes,
@@ -265,7 +263,7 @@ static void lpuart_prepare_tx(struct lpuart_port *sport) 
	if (!count)

		return;



	if (count < DMA_MAXBURST)

	if (count < sport->txfifo_size)

		writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS,

				sport->port.membase + UARTCR5);

	else {
@@ -595,15 +593,7 @@ static void lpuart_setup_watermark(struct lpuart_port *sport) 
			UARTCR2_RIE | UARTCR2_RE);

	writeb(cr2, sport->port.membase + UARTCR2);



	/* determine FIFO size and enable FIFO mode */

	val = readb(sport->port.membase + UARTPFIFO);



	sport->txfifo_size = 0x1 << (((val >> UARTPFIFO_TXSIZE_OFF) &

		UARTPFIFO_FIFOSIZE_MASK) + 1);



	sport->rxfifo_size = 0x1 << (((val >> UARTPFIFO_RXSIZE_OFF) &

		UARTPFIFO_FIFOSIZE_MASK) + 1);



	writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,

			sport->port.membase + UARTPFIFO);
@@ -648,7 +638,7 @@ static int lpuart_dma_tx_request(struct uart_port *port) 
	dma_buf = sport->port.state->xmit.buf;

	dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;

	dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;

	dma_tx_sconfig.dst_maxburst = DMA_MAXBURST;

	dma_tx_sconfig.dst_maxburst = sport->txfifo_size;

	dma_tx_sconfig.direction = DMA_MEM_TO_DEV;

	ret = dmaengine_slave_config(tx_chan, &dma_tx_sconfig);
@@ -761,7 +751,16 @@ static int lpuart_startup(struct uart_port *port) 
	unsigned long flags;

	unsigned char temp;



	/*whether use dma support by dma request results*/

	/* determine FIFO size and enable FIFO mode */

	temp = readb(sport->port.membase + UARTPFIFO);



	sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) &

		UARTPFIFO_FIFOSIZE_MASK) + 1);



	sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) &

		UARTPFIFO_FIFOSIZE_MASK) + 1);



	/* Whether use dma support by dma request results */

	if (lpuart_dma_tx_request(port) || lpuart_dma_rx_request(port)) {

		sport->lpuart_dma_use = false;

	} else {

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