Commit ed9705e4 authored Sep 29, 2020 by Tony Luck Committed by Borislav Petkov Sep 30, 2020

x86/mce: Drop AMD-specific "DEFERRED" case from Intel severity rule list



Way back in v3.19 Intel and AMD shared the same machine check severity
grading code. So it made sense to add a case for AMD DEFERRED errors in
commit

  e3480271 ("x86, mce, severity: Extend the the mce_severity mechanism to handle UCNA/DEFERRED error")

But later in v4.2 AMD switched to a separate grading function in
commit

  bf80bbd7 ("x86/mce: Add an AMD severities-grading function")

Belatedly drop the DEFERRED case from the Intel rule list.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20200930021313.31810-3-tony.luck@intel.com

parent fd258dc4

arch/x86/kernel/cpu/mce/severity.c

+0 −4

Original line number	Diff line number	Diff line
		@@ -96,10 +96,6 @@ static struct severity {
		PANIC, "In kernel and no restart IP",
		EXCP, KERNEL_RECOV, MCGMASK(MCG_STATUS_RIPV, 0)
		),
		MCESEV(
		DEFERRED, "Deferred error",
		NOSER, MASK(MCI_STATUS_UC\|MCI_STATUS_DEFERRED\|MCI_STATUS_POISON, MCI_STATUS_DEFERRED)
		),
		MCESEV(
		KEEP, "Corrected error",
		NOSER, BITCLR(MCI_STATUS_UC)

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