Commit ed852cde authored by Hans de Goede's avatar Hans de Goede Committed by Rafael J. Wysocki
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ACPI / PMIC: Add byt prefix to Crystal Cove PMIC OpRegion driver 



Our current Crystal Cove OpRegion driver is only valid for the
Crystal Cove PMIC variant found on Bay Trail (BYT) boards,
Cherry Trail (CHT) based boards use another variant.

At least the regulator registers are different on CHT and these registers
are one of the things controlled by the custom PMIC OpRegion.

Commit 4d9ed62a ("mfd: intel_soc_pmic: Export separate mfd-cell
configs for BYT and CHT") has disabled the intel_pmic_crc.c code for CHT
devices by removing the "crystal_cove_pmic" MFD cell on CHT devices.

This commit renames the intel_pmic_crc.c driver and the cell to be
prefixed with "byt" to indicate that this code is for BYT devices only.

This is a preparation patch for adding a separate PMIC OpRegion
driver for the CHT variant of the Crystal Cove PMIC (sometimes called
Crystal Cove Plus in Android kernel sources).

Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent a0fcfed1

drivers/acpi/Kconfig

+4 −3
Original line number Diff line number Diff line
@@ -513,11 +513,12 @@ menuconfig PMIC_OPREGION 
	  PMIC chip.



if PMIC_OPREGION

config CRC_PMIC_OPREGION

	bool "ACPI operation region support for CrystalCove PMIC"

config BYTCRC_PMIC_OPREGION

	bool "ACPI operation region support for Bay Trail Crystal Cove PMIC"

	depends on INTEL_SOC_PMIC

	help

	  This config adds ACPI operation region support for CrystalCove PMIC.

	  This config adds ACPI operation region support for the Bay Trail

	  version of the Crystal Cove PMIC.



config XPOWER_PMIC_OPREGION

	bool "ACPI operation region support for XPower AXP288 PMIC"

drivers/acpi/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -109,7 +109,7 @@ obj-$(CONFIG_ACPI_APEI) += apei/ 
obj-$(CONFIG_ACPI_EXTLOG)	+= acpi_extlog.o



obj-$(CONFIG_PMIC_OPREGION)	+= pmic/intel_pmic.o

obj-$(CONFIG_CRC_PMIC_OPREGION) += pmic/intel_pmic_crc.o

obj-$(CONFIG_BYTCRC_PMIC_OPREGION) += pmic/intel_pmic_bytcrc.o

obj-$(CONFIG_XPOWER_PMIC_OPREGION) += pmic/intel_pmic_xpower.o

obj-$(CONFIG_BXT_WC_PMIC_OPREGION) += pmic/intel_pmic_bxtwc.o

obj-$(CONFIG_CHT_WC_PMIC_OPREGION) += pmic/intel_pmic_chtwc.o

drivers/acpi/pmic/intel_pmic_crc.c→drivers/acpi/pmic/intel_pmic_bytcrc.c

+2 −2
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Intel CrystalCove PMIC operation region driver

 * Intel Bay Trail Crystal Cove PMIC operation region driver

 *

 * Copyright (C) 2014 Intel Corporation. All rights reserved.

 */
@@ -295,7 +295,7 @@ static int intel_crc_pmic_opregion_probe(struct platform_device *pdev) 
static struct platform_driver intel_crc_pmic_opregion_driver = {

	.probe = intel_crc_pmic_opregion_probe,

	.driver = {

		.name = "crystal_cove_pmic",

		.name = "byt_crystal_cove_pmic",

	},

};

builtin_platform_driver(intel_crc_pmic_opregion_driver);

drivers/mfd/intel_soc_pmic_crc.c

+1 −1
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ static struct mfd_cell crystal_cove_byt_dev[] = { 
		.resources = gpio_resources,

	},

	{

		.name = "crystal_cove_pmic",

		.name = "byt_crystal_cove_pmic",

	},

	{

		.name = "crystal_cove_pwm",

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