Commit ed54d954 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/pp: fix copy paste typo in smu7_get_pp_table_entry_callback_func_v1 



Should be using PCIELaneLow for the low clock level.

Reviewed-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9861023c

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+1 −1
Original line number Diff line number Diff line
@@ -3183,7 +3183,7 @@ static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr, 
	performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,

			state_entry->ucPCIEGenLow);

	performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,

			state_entry->ucPCIELaneHigh);

			state_entry->ucPCIELaneLow);



	performance_level = &(smu7_power_state->performance_levels

			[smu7_power_state->performance_level_count++]);

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