Unverified Commit ed443341 authored Nov 04, 2018 by Jernej Skrabec Committed by Maxime Ripard Nov 05, 2018

clk: sunxi-ng: h6: Set video PLLs limits

Video PLL factors can be set in a way that final PLL rate is outside
stable range. H6 user manual specifically says that N factor should not
be below 12. While it doesn't says anything about maximum stable rate, it
is clear that PLL doesn't work at 6.096 GHz (254 * 24 MHz).

Set minimum allowed PLL video rate to 288 MHz (12 * 24 MHz) and maximum
to 2.4 GHz, which is maximum in BSP driver.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

parent 65b66576

drivers/clk/sunxi-ng/ccu-sun50i-h6.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -120,6 +120,8 @@ static struct ccu_nm pll_video0_clk = {
		.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
		.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
		.fixed_post_div = 4,
		.min_rate = 288000000,
		.max_rate = 2400000000UL,
		.common = {
		.reg = 0x040,
		.features = CCU_FEATURE_FIXED_POSTDIV,
		@@ -136,6 +138,8 @@ static struct ccu_nm pll_video1_clk = {
		.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
		.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
		.fixed_post_div = 4,
		.min_rate = 288000000,
		.max_rate = 2400000000UL,
		.common = {
		.reg = 0x048,
		.features = CCU_FEATURE_FIXED_POSTDIV,

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