Commit ed2de9f7 authored by Will Deacon's avatar Will Deacon Committed by Ingo Molnar
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locking/Documentation: Clarify failed cmpxchg() memory ordering semantics 



A failed cmpxchg does not provide any memory ordering guarantees, a
property that is used to optimise the cmpxchg implementations on Alpha,
PowerPC and arm64.

This patch updates atomic_ops.txt and memory-barriers.txt to reflect
this.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Davidlohr Bueso <dave@stgolabs.net>
Cc: Douglas Hatch <doug.hatch@hp.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Scott J Norton <scott.norton@hp.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Waiman Long <waiman.long@hp.com>
Link: http://lkml.kernel.org/r/20150716151006.GH26390@arm.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 0b792bf5

Documentation/atomic_ops.txt

+3 −1
Original line number Diff line number Diff line
@@ -266,7 +266,9 @@ with the given old and new values. Like all atomic_xxx operations, 
atomic_cmpxchg will only satisfy its atomicity semantics as long as all

other accesses of *v are performed through atomic_xxx operations.



atomic_cmpxchg must provide explicit memory barriers around the operation.

atomic_cmpxchg must provide explicit memory barriers around the operation,

although if the comparison fails then no memory ordering guarantees are

required.



The semantics for atomic_cmpxchg are the same as those defined for 'cas'

below.

Documentation/memory-barriers.txt

+3 −3
Original line number Diff line number Diff line
@@ -2383,9 +2383,7 @@ about the state (old or new) implies an SMP-conditional general memory barrier 
explicit lock operations, described later).  These include:



	xchg();

	cmpxchg();

	atomic_xchg();			atomic_long_xchg();

	atomic_cmpxchg();		atomic_long_cmpxchg();

	atomic_inc_return();		atomic_long_inc_return();

	atomic_dec_return();		atomic_long_dec_return();

	atomic_add_return();		atomic_long_add_return();
@@ -2398,7 +2396,9 @@ explicit lock operations, described later). These include: 
	test_and_clear_bit();

	test_and_change_bit();



	/* when succeeds (returns 1) */

	/* when succeeds */

	cmpxchg();

	atomic_cmpxchg();		atomic_long_cmpxchg();

	atomic_add_unless();		atomic_long_add_unless();



These are used for such things as implementing ACQUIRE-class and RELEASE-class

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