Commit ed2ca6ee authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-dt-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt 

From Shawn Guo:

imx device tree changes for 3.11:

* A bunch of new board additions, imx6sl-evk, vf610-twr, imx53-tx53,
  imx53-m53evk and imx27-phytec-phycore
* Various pinctrl setting updates and additions
* Enable various on board peripherals, usb, audio, nor, display etc.
* Configure L2 cache data and tag latency from device tree
* Add imx-weim bus driver

* tag 'imx-dt-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6

: (82 commits)
  ARM: dts: imx27: Add VPU devicetree node
  ARM: mxc: fix gpio-ranges for VF610
  ARM: dtsi: imx6qdl-sabresd: Enable WM8962 audio support
  ARM: dtsi: imx6qdl-sabresd: Enable SSI2 and AUDMUX
  ARM: dtsi: imx6qdl-sabresd: Add WM8962 CODEC support
  ARM: dtsi: imx6qdl-sabresd: add a fixed regulator for WM8962
  ARM: dtsi: imx6dl: Add a pinctrl for AUDMUX
  ARM: dtsi: imx6q/imx6dl: Add a pinctrl for I2C1
  ARM: dts: imx6qdl-sabresd: add clko1 iomux configuration
  ARM: dts: Phytec imx6q pfla02 and pbab01 support
  ARM: dts: imx6q: Add pinctrl for usdhc2 and enet
  ARM: dts: imx27-phytec-phycore-rdk: Add MTD name for NOR flash
  ARM: dts: imx27-phytec-phycore-rdk: Add SDHC support
  ARM: dts: i.MX27: Add SDHC devicetree nodes
  ARM: dts: i.MX27: Add DMA devicetree node
  ARM: dts: imx6qdl-sabreauto: enable the WEIM NOR
  ARM: dts: imx6dl: add pinctrls for WEIM NOR
  ARM: dts: imx6q: add pinctrls for WEIM NOR
  ARM: dts: imx6qdl: add more information for WEIM
  ARM: dts: imx6q{dl}: fix the pin conflict between SPI and WEIM
  ...

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents f25a4d68 93b331ce

Documentation/devicetree/bindings/bus/imx-weim.txt

0 → 100644
+49 −0
Original line number Diff line number Diff line 
Device tree bindings for i.MX Wireless External Interface Module (WEIM)



The term "wireless" does not imply that the WEIM is literally an interface

without wires. It simply means that this module was originally designed for

wireless and mobile applications that use low-power technology.



The actual devices are instantiated from the child nodes of a WEIM node.



Required properties:



 - compatible:		Should be set to "fsl,imx6q-weim"

 - reg:			A resource specifier for the register space

			(see the example below)

 - clocks:		the clock, see the example below.

 - #address-cells:	Must be set to 2 to allow memory address translation

 - #size-cells:		Must be set to 1 to allow CS address passing

 - ranges:		Must be set up to reflect the memory layout with four

			integer values for each chip-select line in use:



			   <cs-number> 0 <physical address of mapping> <size>



Timing property for child nodes. It is mandatory, not optional.



 - fsl,weim-cs-timing:	The timing array, contains 6 timing values for the

			child node. We can get the CS index from the child

			node's "reg" property. This property contains the values

			for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1,

			EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.



Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:



	weim: weim@021b8000 {

		compatible = "fsl,imx6q-weim";

		reg = <0x021b8000 0x4000>;

		clocks = <&clks 196>;

		#address-cells = <2>;

		#size-cells = <1>;

		ranges = <0 0 0x08000000 0x08000000>;



		nor@0,0 {

			compatible = "cfi-flash";

			reg = <0 0 0x02000000>;

			#address-cells = <1>;

			#size-cells = <1>;

			bank-width = <2>;

			fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000

					0x0000c000 0x1404a38e 0x00000000>;

		};

	};

Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt

+1 −1
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ Some requirements for using fsl,imx-pinctrl binding: 


Examples:

usdhc@0219c000 { /* uSDHC4 */

	fsl,card-wired;

	non-removable;

	vmmc-supply = <&reg_3p3v>;

	status = "okay";

	pinctrl-names = "default";

arch/arm/boot/dts/Makefile

+7 −2
Original line number Diff line number Diff line
@@ -107,13 +107,15 @@ dtb-$(CONFIG_ARCH_MXC) += \ 
	imx27-apf27.dtb \

	imx27-apf27dev.dtb \

	imx27-pdk.dtb \

	imx27-phytec-phycore.dtb \

	imx27-phytec-phycore-som.dtb \

	imx27-phytec-phycore-rdk.dtb \

	imx31-bug.dtb \

	imx51-apf51.dtb \

	imx51-apf51dev.dtb \

	imx51-babbage.dtb \

	imx53-ard.dtb \

	imx53-evk.dtb \

	imx53-m53evk.dtb \

	imx53-mba53.dtb \

	imx53-qsb.dtb \

	imx53-smd.dtb \
@@ -121,10 +123,13 @@ dtb-$(CONFIG_ARCH_MXC) += \ 
	imx6dl-sabresd.dtb \

	imx6dl-wandboard.dtb \

	imx6q-arm2.dtb \

	imx6q-phytec-pbab01.dtb \

	imx6q-sabreauto.dtb \

	imx6q-sabrelite.dtb \

	imx6q-sabresd.dtb \

	imx6q-sbc6x.dtb

	imx6q-sbc6x.dtb \

	imx6sl-evk.dtb \

	vf610-twr.dtb

dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \

	imx23-olinuxino.dtb \

	imx23-stmp378x_devb.dtb \

arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts

0 → 100644
+37 −0
Original line number Diff line number Diff line 
/*

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */



#include "imx27-phytec-phycore-som.dts"



/ {

	model = "Phytec pcm970";

	compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";

};



&cspi1 {

	fsl,spi-num-chipselects = <2>;

	cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>;

};



&sdhci2 {

	bus-width = <4>;

	cd-gpios = <&gpio3 29 0>;

	wp-gpios = <&gpio3 28 0>;

	vmmc-supply = <&vmmc1_reg>;

	status = "okay";

};



&uart1 {

	fsl,uart-has-rtscts;

};



&uart2 {

	fsl,uart-has-rtscts;

	status = "okay";

};

arch/arm/boot/dts/imx27-phytec-phycore.dts→arch/arm/boot/dts/imx27-phytec-phycore-som.dts

+179 −0
Original line number Diff line number Diff line
@@ -23,17 +23,6 @@ 
	soc {

		aipi@10000000 { /* aipi1 */

			serial@1000a000 {

				fsl,uart-has-rtscts;

				status = "okay";

			};



			serial@1000b000 {

				fsl,uart-has-rtscts;

				status = "okay";

			};



			serial@1000c000 {

				fsl,uart-has-rtscts;

				status = "okay";

			};
@@ -58,6 +47,7 @@ 


		aipi@10020000 { /* aipi2 */

			ethernet@1002b000 {

				phy-reset-gpios = <&gpio3 30 0>;

				status = "okay";

			};

		};
@@ -67,11 +57,121 @@ 
		compatible = "cfi-flash";

		bank-width = <2>;

		reg = <0xc0000000 0x02000000>;

		linux,mtd-name = "physmap-flash.0";

		#address-cells = <1>;

		#size-cells = <1>;

	};

};



&cspi1 {

	fsl,spi-num-chipselects = <1>;

	cs-gpios = <&gpio4 28 0>;

	status = "okay";



	pmic: mc13783@0 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "fsl,mc13783";

		spi-max-frequency = <20000000>;

		reg = <0>;

		interrupt-parent = <&gpio2>;

		interrupts = <23 0x4>;

		fsl,mc13xxx-uses-adc;

		fsl,mc13xxx-uses-rtc;



		regulators {

			sw1a_reg: sw1a {

				regulator-min-microvolt = <1200000>;

				regulator-max-microvolt = <1200000>;

				regulator-always-on;

				regulator-boot-on;

			};



			sw1b_reg: sw1b {

				regulator-min-microvolt = <1200000>;

				regulator-max-microvolt = <1200000>;

				regulator-always-on;

				regulator-boot-on;

			};



			sw2a_reg: sw2a {

				regulator-min-microvolt = <1800000>;

				regulator-max-microvolt = <1800000>;

				regulator-always-on;

				regulator-boot-on;

			};



			sw2b_reg: sw2b {

				regulator-min-microvolt = <1800000>;

				regulator-max-microvolt = <1800000>;

				regulator-always-on;

				regulator-boot-on;

			};



			sw3_reg: sw3 {

				regulator-min-microvolt = <5000000>;

				regulator-max-microvolt = <5000000>;

				regulator-always-on;

				regulator-boot-on;

			};



			vaudio_reg: vaudio {

				regulator-always-on;

				regulator-boot-on;

			};



			violo_reg: violo {

				regulator-min-microvolt = <1800000>;

				regulator-max-microvolt = <1800000>;

				regulator-always-on;

				regulator-boot-on;

			};



			viohi_reg: viohi {

				regulator-always-on;

				regulator-boot-on;

			};



			vgen_reg: vgen {

				regulator-min-microvolt = <1500000>;

				regulator-max-microvolt = <1500000>;

				regulator-always-on;

				regulator-boot-on;

			};



			vcam_reg: vcam {

				regulator-min-microvolt = <2800000>;

				regulator-max-microvolt = <2800000>;

			};



			vrf1_reg: vrf1 {

				regulator-min-microvolt = <2775000>;

				regulator-max-microvolt = <2775000>;

				regulator-always-on;

				regulator-boot-on;

			};



			vrf2_reg: vrf2 {

				regulator-min-microvolt = <2775000>;

				regulator-max-microvolt = <2775000>;

				regulator-always-on;

				regulator-boot-on;

			};



			vmmc1_reg: vmmc1 {

				regulator-min-microvolt = <1600000>;

				regulator-max-microvolt = <3000000>;

			};



			gpo1_reg: gpo1 { };



			pwgt1spi_reg: pwgt1spi {

				regulator-always-on;

			};

		};

	};

};



&nfc {

	nand-bus-width = <8>;

	nand-ecc-mode = "hw";

CRA Git | Maintained and supported by SUSTech CRA and CCSE