Commit ed19b739 authored by Will Deacon's avatar Will Deacon Committed by Russell King
Browse files

ARM: 6656/1: hw_breakpoint: avoid UNPREDICTABLE behaviour when reading DBGDSCR 



Reading baseline CP14 registers, other than DBGDIDR, when the OS Lock
is set leads to UNPREDICTABLE behaviour.

This patch ensures that we clear the OS lock before accessing anything
other than the DBGDIDR, thereby avoiding this behaviour.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 34cd2d38

arch/arm/kernel/hw_breakpoint.c

+13 −13
Original line number Diff line number Diff line
@@ -834,11 +834,11 @@ static void reset_ctrl_regs(void *unused) 


	/*

	 * v7 debug contains save and restore registers so that debug state

	 * can be maintained across low-power modes without leaving

	 * the debug logic powered up. It is IMPLEMENTATION DEFINED whether

	 * we can write to the debug registers out of reset, so we must

	 * unlock the OS Lock Access Register to avoid taking undefined

	 * instruction exceptions later on.

	 * can be maintained across low-power modes without leaving the debug

	 * logic powered up. It is IMPLEMENTATION DEFINED whether we can access

	 * the debug registers out of reset, so we must unlock the OS Lock

	 * Access Register to avoid taking undefined instruction exceptions

	 * later on.

	 */

	if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) {

		/*
@@ -899,18 +899,18 @@ static int __init arch_hw_breakpoint_init(void) 
		pr_info("%d breakpoint(s) reserved for watchpoint "

				"single-step.\n", core_num_reserved_brps);



	ARM_DBG_READ(c1, 0, dscr);

	if (dscr & ARM_DSCR_HDBGEN) {

		pr_warning("halting debug mode enabled. Assuming maximum "

				"watchpoint size of 4 bytes.");

	} else {

	/*

	 * Reset the breakpoint resources. We assume that a halting

	 * debugger will leave the world in a nice state for us.

	 */

		smp_call_function(reset_ctrl_regs, NULL, 1);

		reset_ctrl_regs(NULL);

	on_each_cpu(reset_ctrl_regs, NULL, 1);



	ARM_DBG_READ(c1, 0, dscr);

	if (dscr & ARM_DSCR_HDBGEN) {

		max_watchpoint_len = 4;

		pr_warning("halting debug mode enabled. Assuming maximum "

			   "watchpoint size of %u bytes.", max_watchpoint_len);

	} else {

		/* Work out the maximum supported watchpoint length. */

		max_watchpoint_len = get_max_wp_len();

		pr_info("maximum watchpoint size is %u bytes.\n",

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