Merge tag 'phy-for-4.21_v1' of...

- cpsw-phy-sel		: Specifies the phandle to the CPSW phy mode selection

			  device. See also cpsw-phy-sel.txt for it's binding.

			  Note that in legacy cases cpsw-phy-sel may be

			  a child device instead of a phandle.

			  a child device instead of a phandle

			  (DEPRECATED, use phys property instead).

Optional properties:

- ti,hwmods		: Must be "cpgmac0"

Slave Properties:

Required properties:

- phy-mode		: See ethernet.txt file in the same directory

- phys			: phandle on phy-gmii-sel PHY (see phy/ti-phy-gmii-sel.txt)

Optional properties:

- dual_emac_res_vlan	: Specifies VID to be used to segregate the ports

			phy-mode = "rgmii-txid";

			/* Filled in by U-Boot */

			mac-address = [ 00 00 00 00 00 00 ];

			phys = <&phy_gmii_sel 1 0>;

		};

		cpsw_emac1: slave@1 {

			phy_id = <&davinci_mdio>, <1>;

			phy-mode = "rgmii-txid";

			/* Filled in by U-Boot */

			mac-address = [ 00 00 00 00 00 00 ];

			phys = <&phy_gmii_sel 2 0>;

		};

	};

			phy-mode = "rgmii-txid";

			/* Filled in by U-Boot */

			mac-address = [ 00 00 00 00 00 00 ];

			phys = <&phy_gmii_sel 1 0>;

		};

		cpsw_emac1: slave@1 {

			phy_id = <&davinci_mdio>, <1>;

			phy-mode = "rgmii-txid";

			/* Filled in by U-Boot */

			mac-address = [ 00 00 00 00 00 00 ];

			phys = <&phy_gmii_sel 2 0>;

		};

	};

* Freescale i.MX8MQ USB3 PHY binding

Required properties:

- compatible:	Should be "fsl,imx8mq-usb-phy"

- #phys-cells:	must be 0 (see phy-bindings.txt in this directory)

- reg:		The base address and length of the registers

- clocks:	phandles to the clocks for each clock listed in clock-names

- clock-names:	must contain "phy"

Example:

	usb3_phy0: phy@381f0040 {

		compatible = "fsl,imx8mq-usb-phy";

		reg = <0x381f0040 0x40>;

		clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;

		clock-names = "phy";

		#phy-cells = <0>;

	};

Cadence Sierra PHY

-----------------------

Required properties:

- compatible:	cdns,sierra-phy-t0

- clocks:	Must contain an entry in clock-names.

		See ../clocks/clock-bindings.txt for details.

- clock-names:	Must be "phy_clk"

- resets:	Must contain an entry for each in reset-names.

		See ../reset/reset.txt for details.

- reset-names:	Must include "sierra_reset" and "sierra_apb".

		"sierra_reset" must control the reset line to the PHY.

		"sierra_apb" must control the reset line to the APB PHY

		interface.

- reg:		register range for the PHY.

- #address-cells: Must be 1

- #size-cells:	Must be 0

Optional properties:

- cdns,autoconf:	A boolean property whose presence indicates that the

			PHY registers will be configured by hardware. If not

			present, all sub-node optional properties must be

			provided.

Sub-nodes:

  Each group of PHY lanes with a single master lane should be represented as

  a sub-node. Note that the actual configuration of each lane is determined by

  hardware strapping, and must match the configuration specified here.

Sub-node required properties:

- #phy-cells:	Generic PHY binding; must be 0.

- reg:		The master lane number.  This is the lowest numbered lane

		in the lane group.

- resets:	Must contain one entry which controls the reset line for the

		master lane of the sub-node.

		See ../reset/reset.txt for details.

Sub-node optional properties:

- cdns,num-lanes:	Number of lanes in this group.  From 1 to 4.  The

			group is made up of consecutive lanes.

- cdns,phy-type:	Can be PHY_TYPE_PCIE or PHY_TYPE_USB3, depending on

			configuration of lanes.

Example:

	pcie_phy4: pcie-phy@fd240000 {

		compatible = "cdns,sierra-phy-t0";

		reg = <0x0 0xfd240000 0x0 0x40000>;

		resets = <&phyrst 0>, <&phyrst 1>;

		reset-names = "sierra_reset", "sierra_apb";

		clocks = <&phyclock>;

		clock-names = "phy_clk";

		#address-cells = <1>;

		#size-cells = <0>;

		pcie0_phy0: pcie-phy@0 {

				reg = <0>;

				resets = <&phyrst 2>;

				cdns,num-lanes = <2>;

				#phy-cells = <0>;

				cdns,phy-type = <PHY_TYPE_PCIE>;

		};

		pcie0_phy1: pcie-phy@2 {

				reg = <2>;

				resets = <&phyrst 4>;

				cdns,num-lanes = <1>;

				#phy-cells = <0>;

				cdns,phy-type = <PHY_TYPE_PCIE>;

		};

  - For all others:

    - The reg-names property shouldn't be defined.

 - #clock-cells: must be 1

    - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe

      interface (for pipe based PHYs). These clock are then gate-controlled

      by gcc.

 - #address-cells: must be 1

 - #size-cells: must be 1

 - ranges: must be present

 - Each device node of QMP phy is required to have as many child nodes as

   the number of lanes the PHY has.

Required properties for child node:

Required properties for child nodes of PCIe PHYs (one child per lane):

 - reg: list of offset and length pairs of register sets for PHY blocks -

	- index 0: tx

	- index 1: rx

	- index 2: pcs

	- index 3: pcs_misc (optional)

	tx, rx, pcs, and pcs_misc (optional).

 - #phy-cells: must be 0

Required properties for a single "lanes" child node of non-PCIe PHYs:

 - reg: list of offset and length pairs of register sets for PHY blocks

	For 1-lane devices:

		tx, rx, pcs, and (optionally) pcs_misc

	For 2-lane devices:

		tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc

 - #phy-cells: must be 0

Required properties child node of pcie and usb3 qmp phys:

Required properties for child node of PCIe and USB3 qmp phys:

 - clocks: a list of phandles and clock-specifier pairs,

	   one for each entry in clock-names.

 - clock-names: Must contain following:

		 "pipe<lane-number>" for pipe clock specific to each lane.

 - clock-output-names: Name of the PHY clock that will be the parent for

		       the above pipe clock.

	For "qcom,ipq8074-qmp-pcie-phy":

		- "pcie20_phy0_pipe_clk"	Pipe Clock parent

			(or)

		  "pcie20_phy1_pipe_clk"

 - #clock-cells: must be 0

    - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then

      gate-controlled by the gcc.

Required properties for child node of PHYs with lane reset, AKA:

	"qcom,msm8996-qmp-pcie-phy"

	phy@34000 {

		compatible = "qcom,msm8996-qmp-pcie-phy";

		reg = <0x34000 0x488>;

		#clock-cells = <1>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

			reg = <0x35000 0x130>,

				<0x35200 0x200>,

				<0x35400 0x1dc>;

			#clock-cells = <0>;

			#phy-cells = <0>;

			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;

		...

		...

	};

	phy@88eb000 {

		compatible = "qcom,sdm845-qmp-usb3-uni-phy";

		reg = <0x88eb000 0x18c>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,

			 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

			 <&gcc GCC_USB3_SEC_CLKREF_CLK>,

			 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;

		clock-names = "aux", "cfg_ahb", "ref", "com_aux";

		resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,

			 <&gcc GCC_USB3_PHY_SEC_BCR>;

		reset-names = "phy", "common";

		lane@88eb200 {

			reg = <0x88eb200 0x128>,

			      <0x88eb400 0x1fc>,

			      <0x88eb800 0x218>,

			      <0x88eb600 0x70>;

			#clock-cells = <0>;

			#phy-cells = <0>;

			clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;

			clock-names = "pipe0";

			clock-output-names = "usb3_uni_phy_pipe_clk_src";

		};

	};

	phy@1d87000 {

		compatible = "qcom,sdm845-qmp-ufs-phy";

		reg = <0x1d87000 0x18c>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		clock-names = "ref",

			      "ref_aux";

		clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,

			 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

		lanes@1d87400 {

			reg = <0x1d87400 0x108>,

			      <0x1d87600 0x1e0>,

			      <0x1d87c00 0x1dc>,

			      <0x1d87800 0x108>,

			      <0x1d87a00 0x1e0>;

			#phy-cells = <0>;

		};

	};

  * allwinner,sun8i-r40-usb-phy

  * allwinner,sun8i-v3s-usb-phy

  * allwinner,sun50i-a64-usb-phy

  * allwinner,sun50i-h6-usb-phy

- reg : a list of offset + length pairs

- reg-names :

  * "phy_ctrl"

  * "pmu0" for H3, V3s and A64

  * "pmu0" for H3, V3s, A64 or H6

  * "pmu1"

  * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3

  * "pmu3" for sun8i-h3

  * "pmu3" for sun8i-h3 or sun50i-h6

- #phy-cells : from the generic phy bindings, must be 1

- clocks : phandle + clock specifier for the phy clocks

- clock-names :

  * "usb0_phy", "usb1_phy" for sun8i

  * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t

  * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3

  * "usb0_phy" and "usb3_phy" for sun50i-h6

- resets : a list of phandle + reset specifier pairs

- reset-names :

  * "usb0_reset"

  * "usb1_reset"

  * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3

  * "usb3_reset" for sun8i-h3

  * "usb3_reset" for sun8i-h3 and sun50i-h6

Optional properties:

- usb0_id_det-gpios : gpio phandle for reading the otg id pin value