Commit ecdeca6d authored by Suman Anna's avatar Suman Anna Committed by Tony Lindgren
Browse files

ARM: dts: dra7: Add PRU-ICSS interconnect target-module nodes 



The AM57xx family of SoCs contains two identical PRU-ICSS instances
that have a very unique SYSC register. The IPs do not have any
PRCM reset lines unlike those on AM33xx/AM437x SoCs. Add the PRUSS
interconnect target-module nodes with all the required properties.

Each of the PRUSS devices themselves shall be added as child nodes
to the corresponding interconnect node in the future. The PRU-ICSS
instances are only available on AM57xx family of SoCs and are not
supported on DRA7xx family of SoCs in general, so the target module
nodes are added in a separate dtsi file. This new dtsi file is
included in all the AM57xx SoC dtsi files, so the nodes are
automatically inherited and enabled on all AM57xx boards.

Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 44e66a5d

arch/arm/boot/dts/am57-pruss.dtsi

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// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/

 *

 * Common PRUSS data for TI AM57xx platforms

 */



&ocp {

	pruss1_tm: target-module@4b226000 {

		compatible = "ti,sysc-pruss", "ti,sysc";

		reg = <0x4b226000 0x4>,

		      <0x4b226004 0x4>;

		reg-names = "rev", "sysc";

		ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |

				 SYSC_PRUSS_SUB_MWAIT)>;

		ti,sysc-midle = <SYSC_IDLE_FORCE>,

				<SYSC_IDLE_NO>,

				<SYSC_IDLE_SMART>;

		ti,sysc-sidle = <SYSC_IDLE_FORCE>,

				<SYSC_IDLE_NO>,

				<SYSC_IDLE_SMART>;

		/* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */

		clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>;

		clock-names = "fck";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x4b200000 0x80000>;

	};



	pruss2_tm: target-module@4b2a6000 {

		compatible = "ti,sysc-pruss", "ti,sysc";

		reg = <0x4b2a6000 0x4>,

		      <0x4b2a6004 0x4>;

		reg-names = "rev", "sysc";

		ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |

				 SYSC_PRUSS_SUB_MWAIT)>;

		ti,sysc-midle = <SYSC_IDLE_FORCE>,

				<SYSC_IDLE_NO>,

				<SYSC_IDLE_SMART>;

		ti,sysc-sidle = <SYSC_IDLE_FORCE>,

				<SYSC_IDLE_NO>,

				<SYSC_IDLE_SMART>;

		/* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */

		clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS2_CLKCTRL 0>;

		clock-names = "fck";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x4b280000 0x80000>;

	};

};

arch/arm/boot/dts/am5718.dtsi

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@@ -4,6 +4,7 @@ 
 */



#include "dra72x.dtsi"

#include "am57-pruss.dtsi"



/ {

	compatible = "ti,am5718", "ti,dra7";

arch/arm/boot/dts/am5728.dtsi

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@@ -4,6 +4,7 @@ 
 */



#include "dra74x.dtsi"

#include "am57-pruss.dtsi"



/ {

	compatible = "ti,am5728", "ti,dra7";

arch/arm/boot/dts/am5748.dtsi

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@@ -4,6 +4,7 @@ 
 */



#include "dra76x.dtsi"

#include "am57-pruss.dtsi"



/ {

	compatible = "ti,am5748", "ti,dra762", "ti,dra7";

arch/arm/boot/dts/dra7.dtsi

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@@ -143,7 +143,7 @@ 
	 * the moment, just use a fake OCP bus entry to represent the whole bus

	 * hierarchy.

	 */

	ocp {

	ocp: ocp {

		compatible = "ti,dra7-l3-noc", "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

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