drm/amdgpu: workaround tonga HW bug in HQD programming sequence (ecd910eb) · Commits · 戴 / test

Tonga based asics may experience hangs when an HQD's EOP parameters are modified. Workaround this HW issue by avoiding writes to these registers for tonga asics. Based on the following ROCm commit: 2a0fb8 - drm/amdgpu: Synchronize KFD HQD load protocol with CP scheduler From the ROCm git repository: https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver.git CC: Jay Cornwall <Jay.Cornwall@amd.com> Suggested-by:

Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:

Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:

Andres Rodriguez <andresx7@gmail.com> Signed-off-by:

Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+15 −1

Original line number	Diff line number	Diff line
		@@ -5070,7 +5070,21 @@ int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
		WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);

		/* program all HQD registers */
		for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_ERROR; mqd_reg++)
		for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++)
		WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);

		/* Tonga errata: EOP RPTR/WPTR should be left unmodified.
		* This is safe since EOP RPTR==WPTR for any inactive HQD
		* on ASICs that do not support context-save.
		* EOP writes/reads can start anywhere in the ring.
		*/
		if (adev->asic_type != CHIP_TONGA) {
		WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr);
		WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr);
		WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem);
		}

		for (mqd_reg = mmCP_HQD_EOP_EVENTS; mqd_reg <= mmCP_HQD_ERROR; mqd_reg++)
		WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);

		/* activate the HQD */

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