Commit ecd6910d authored by David Cohen's avatar David Cohen Committed by H. Peter Anvin
Browse files

x86, intel-mid: Move Medfield code out of intel-mid.c core file 



In order make the driver more portable and support other Intel MID
(Mobile Internet Device) platforms we need to move Medfield code from
intel-mid.c core to its own mfld.c file.

This patch contains no functional changes.

Signed-off-by: default avatarDavid Cohen <david.a.cohen@linux.intel.com>
Link: http://lkml.kernel.org/r/1387224459-25746-2-git-send-email-david.a.cohen@linux.intel.com


Signed-off-by: default avatarKuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
parent 7e22e911

arch/x86/platform/intel-mid/Makefile

+2 −2
Original line number Diff line number Diff line 
obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o

obj-$(CONFIG_X86_INTEL_MID) += intel_mid_vrtc.o

obj-$(CONFIG_X86_INTEL_MID) += intel-mid.o intel_mid_vrtc.o mfld.o

obj-$(CONFIG_EARLY_PRINTK_INTEL_MID) += early_printk_intel_mid.o



# SFI specific code

ifdef CONFIG_X86_INTEL_MID

obj-$(CONFIG_SFI) += sfi.o device_libs/

arch/x86/platform/intel-mid/intel-mid.c

+2 −35
Original line number Diff line number Diff line
@@ -35,6 +35,8 @@ 
#include <asm/apb_timer.h>

#include <asm/reboot.h>



#include "intel_mid_weak_decls.h"



/*

 * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,

 * cmdline option x86_intel_mid_timer can be used to override the configuration
@@ -61,46 +63,11 @@ enum intel_mid_timer_options intel_mid_timer_options; 
enum intel_mid_cpu_type __intel_mid_cpu_chip;

EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);



static void intel_mid_power_off(void)

{

}



static void intel_mid_reboot(void)

{

	intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0);

}



static unsigned long __init intel_mid_calibrate_tsc(void)

{

	unsigned long fast_calibrate;

	u32 lo, hi, ratio, fsb;



	rdmsr(MSR_IA32_PERF_STATUS, lo, hi);

	pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);

	ratio = (hi >> 8) & 0x1f;

	pr_debug("ratio is %d\n", ratio);

	if (!ratio) {

		pr_err("read a zero ratio, should be incorrect!\n");

		pr_err("force tsc ratio to 16 ...\n");

		ratio = 16;

	}

	rdmsr(MSR_FSB_FREQ, lo, hi);

	if ((lo & 0x7) == 0x7)

		fsb = PENWELL_FSB_FREQ_83SKU;

	else

		fsb = PENWELL_FSB_FREQ_100SKU;

	fast_calibrate = ratio * fsb;

	pr_debug("read penwell tsc %lu khz\n", fast_calibrate);

	lapic_timer_frequency = fsb * 1000 / HZ;

	/* mark tsc clocksource as reliable */

	set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);



	if (fast_calibrate)

		return fast_calibrate;



	return 0;

}



static void __init intel_mid_time_init(void)

{

	sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);

arch/x86/platform/intel-mid/intel_mid_weak_decls.h

0 → 100644
+15 −0
Original line number Diff line number Diff line 
/*

 * intel_mid_weak_decls.h: Weak declarations of intel-mid.c

 *

 * (C) Copyright 2013 Intel Corporation

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License

 * as published by the Free Software Foundation; version 2

 * of the License.

 */





/* __attribute__((weak)) makes these declarations overridable */

extern void intel_mid_power_off(void) __attribute__((weak));

extern unsigned long __init intel_mid_calibrate_tsc(void) __attribute__((weak));

arch/x86/platform/intel-mid/mfld.c

0 → 100644
+51 −0
Original line number Diff line number Diff line 
/*

 * mfld.c: Intel Medfield platform setup code

 *

 * (C) Copyright 2013 Intel Corporation

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License

 * as published by the Free Software Foundation; version 2

 * of the License.

 */



#include <linux/init.h>



#include <asm/apic.h>

#include <asm/intel-mid.h>

#include <asm/intel_mid_vrtc.h>



void intel_mid_power_off(void)

{

}



unsigned long __init intel_mid_calibrate_tsc(void)

{

	unsigned long fast_calibrate;

	u32 lo, hi, ratio, fsb;



	rdmsr(MSR_IA32_PERF_STATUS, lo, hi);

	pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);

	ratio = (hi >> 8) & 0x1f;

	pr_debug("ratio is %d\n", ratio);

	if (!ratio) {

		pr_err("read a zero ratio, should be incorrect!\n");

		pr_err("force tsc ratio to 16 ...\n");

		ratio = 16;

	}

	rdmsr(MSR_FSB_FREQ, lo, hi);

	if ((lo & 0x7) == 0x7)

		fsb = PENWELL_FSB_FREQ_83SKU;

	else

		fsb = PENWELL_FSB_FREQ_100SKU;

	fast_calibrate = ratio * fsb;

	pr_debug("read penwell tsc %lu khz\n", fast_calibrate);

	lapic_timer_frequency = fsb * 1000 / HZ;

	/* mark tsc clocksource as reliable */

	set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);



	if (fast_calibrate)

		return fast_calibrate;



	return 0;

}

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