Commit ecab0f3d authored by Stanislav Lisovskiy's avatar Stanislav Lisovskiy Committed by Ville Syrjälä
Browse files

drm/i915: Track active_pipes in bw_state 



We need to calculate SAGV mask also in a non-modeset
commit, however currently active_pipes are only calculated
for modesets in global atomic state, thus now we will be
tracking those also in bw_state in order to be able to
properly access global data.

v2: - Removed pre/post plane SAGV updates from modeset(Ville)
    - Now tracking active pipes in intel_can_enable_sagv(Ville)

v3: - lock global state if active_pipes change as well(Ville)

Signed-off-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200430195634.7666-1-stanislav.lisovskiy@intel.com
parent 9728889f

drivers/gpu/drm/i915/display/intel_bw.h

+3 −0
Original line number Diff line number Diff line
@@ -26,6 +26,9 @@ struct intel_bw_state { 


	unsigned int data_rate[I915_MAX_PIPES];

	u8 num_active_planes[I915_MAX_PIPES];



	/* bitmask of active pipes */

	u8 active_pipes;

};



#define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base)

drivers/gpu/drm/i915/display/intel_display.c

+4 −5
Original line number Diff line number Diff line
@@ -15379,11 +15379,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) 














		intel_set_cdclk_pre_plane_update(state);



























		intel_sagv_pre_plane_update(state);



























		intel_modeset_verify_disabled(dev_priv, state);















	}



























	intel_sagv_pre_plane_update(state);



























	/* Complete the events for pipes that have now been disabled */















	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {















		bool modeset = needs_modeset(new_crtc_state);










@@ -15476,11 +15476,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)













	intel_check_cpu_fifo_underruns(dev_priv);















	intel_check_pch_fifo_underruns(dev_priv);



























	if (state->modeset) {













	if (state->modeset)















		intel_verify_planes(state);





























	intel_sagv_post_plane_update(state);













	}





























	drm_atomic_helper_commit_hw_done(&state->base);















































drivers/gpu/drm/i915/intel_pm.c



+14
−13






























Original line number
Diff line number
Diff line








@@ -3806,7 +3806,6 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)





























static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)















{













	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);















	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);















	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);















	struct intel_plane *plane;









@@ -3819,13 +3818,6 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state













	if (!crtc_state->hw.active)















		return true;





























	/*













	 * SKL+ workaround: bspec recommends we disable SAGV when we have













	 * more then one pipe enabled













	 */













	if (hweight8(state->active_pipes) > 1)













		return false;





























	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)















		return false;


























@@ -3863,6 +3855,9 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state





























bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)















{













	if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))













		return false;





























	return bw_state->pipe_sagv_reject == 0;















}


























@@ -3892,6 +3887,14 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)













	if (!new_bw_state)















		return 0;





























	new_bw_state->active_pipes =













		intel_calc_active_pipes(state, old_bw_state->active_pipes);













	if (new_bw_state->active_pipes != old_bw_state->active_pipes) {













		ret = intel_atomic_lock_global_state(&new_bw_state->base);













		if (ret)













			return ret;













	}





























	if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {















		ret = intel_atomic_serialize_global_state(&new_bw_state->base);















		if (ret)










@@ -5866,11 +5869,9 @@ skl_compute_wm(struct intel_atomic_state *state)













	if (ret)















		return ret;





























	if (state->modeset) {















	ret = intel_compute_sagv_mask(state);















	if (ret)















		return ret;













	}































	/*















	 * skl_compute_ddb() will have adjusted the final watermarks



































































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