clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock (ec97faff) · Commits · 戴 / test

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

+27 −1

Original line number	Diff line number	Diff line
		@@ -921,11 +921,26 @@ static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {
		.num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets),
		};

		static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {
		.common = &pll_cpux_clk.common,
		/* copy from pll_cpux_clk */
		.enable = BIT(31),
		.lock = BIT(28),
		};

		static struct ccu_mux_nb sun50i_a64_cpu_nb = {
		.common = &cpux_clk.common,
		.cm = &cpux_clk.mux,
		.delay_us = 1, /* > 8 clock cycles at 24 MHz */
		.bypass_index = 1, /* index of 24 MHz oscillator */
		};

		static int sun50i_a64_ccu_probe(struct platform_device *pdev)
		{
		struct resource *res;
		void __iomem *reg;
		u32 val;
		int ret;

		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		reg = devm_ioremap_resource(&pdev->dev, res);
		@@ -939,7 +954,18 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)

		writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);

		return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
		ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);
		if (ret)
		return ret;

		/* Gate then ungate PLL CPU after any rate changes */
		ccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);

		/* Reparent CPU during PLL CPU rate changes */
		ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
		&sun50i_a64_cpu_nb);

		return 0;
		}

		static const struct of_device_id sun50i_a64_ccu_ids[] = {