Commit ec939e4c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull ARM SoC driver updates from Olof Johansson:
 "Various driver updates for platforms:

   - A larger set of work on Tegra 2/3 around memory controller and
     regulator features, some fuse cleanups, etc..

   - MMP platform drivers, in particular for USB PHY, and other smaller
     additions.

   - Samsung Exynos 5422 driver for DMC (dynamic memory configuration),
     and ASV (adaptive voltage), allowing the platform to run at more
     optimal operating points.

   - Misc refactorings and support for RZ/G2N and R8A774B1 from Renesas

   - Clock/reset control driver for TI/OMAP

   - Meson-A1 reset controller support

   - Qualcomm sdm845 and sda845 SoC IDs for socinfo"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (150 commits)
  firmware: arm_scmi: Fix doorbell ring logic for !CONFIG_64BIT
  soc: fsl: add RCPM driver
  dt-bindings: fsl: rcpm: Add 'little-endian' and update Chassis definition
  memory: tegra: Consolidate registers definition into common header
  memory: tegra: Ensure timing control debug features are disabled
  memory: tegra: Introduce Tegra30 EMC driver
  memory: tegra: Do not handle error from wait_for_completion_timeout()
  memory: tegra: Increase handshake timeout on Tegra20
  memory: tegra: Print a brief info message about EMC timings
  memory: tegra: Pre-configure debug register on Tegra20
  memory: tegra: Include io.h instead of iopoll.h
  memory: tegra: Adapt for Tegra20 clock driver changes
  memory: tegra: Don't set EMC rate to maximum on probe for Tegra20
  memory: tegra: Add gr2d and gr3d to DRM IOMMU group
  memory: tegra: Set DMA mask based on supported address bits
  soc: at91: Add Atmel SFR SN (Serial Number) support
  memory: atmel-ebi: switch to SPDX license identifiers
  memory: atmel-ebi: move NUM_CS definition inside EBI driver
  soc: mediatek: Refactor bus protection control
  soc: mediatek: Refactor sram control
  ...
parents 38206c24 3f6939ae

Documentation/arm/microchip.rst

+2 −2
Original line number Diff line number Diff line
@@ -103,7 +103,7 @@ the Microchip website: http://www.microchip.com. 


          * Datasheet



          http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11121-32-bit-Cortex-A5-Microcontroller-SAMA5D3_Datasheet.pdf

          http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11121-32-bit-Cortex-A5-Microcontroller-SAMA5D3_Datasheet_B.pdf



    * ARM Cortex-A5 + NEON based SoCs

      - sama5d4 family
@@ -167,7 +167,7 @@ the Microchip website: http://www.microchip.com. 


          * Datasheet



          http://ww1.microchip.com/downloads/en/DeviceDoc/60001527A.pdf

          http://ww1.microchip.com/downloads/en/DeviceDoc/SAM-E70-S70-V70-V71-Family-Data-Sheet-DS60001527D.pdf





Linux kernel information

Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt

deleted100644 → 0
+0 −41
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== Introduction==



LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,

that can be shared by multiple clients. Clients here are different cores in the

SOC, the idea is to minimize the local caches at the clients and migrate to

common pool of memory. Cache memory is divided into partitions called slices

which are assigned to clients. Clients can query the slice details, activate

and deactivate them.



Properties:

- compatible:

	Usage: required

	Value type: <string>

	Definition: must be "qcom,sdm845-llcc"



- reg:

	Usage: required

	Value Type: <prop-encoded-array>

	Definition: The first element specifies the llcc base start address and

		    the size of the register region. The second element specifies

		    the llcc broadcast base address and size of the register region.



- reg-names:

        Usage: required

        Value Type: <stringlist>

        Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base".



- interrupts:

	Usage: required

	Definition: The interrupt is associated with the llcc edac device.

			It's used for llcc cache single and double bit error detection

			and reporting.



Example:



	cache-controller@1100000 {

		compatible = "qcom,sdm845-llcc";

		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;

		reg-names = "llcc_base", "llcc_broadcast_base";

		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;

	};

Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Last Level Cache Controller



maintainers:

  - Rishabh Bhatnagar <rishabhb@codeaurora.org>

  - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>



description: |

  LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,

  that can be shared by multiple clients. Clients here are different cores in the

  SoC, the idea is to minimize the local caches at the clients and migrate to

  common pool of memory. Cache memory is divided into partitions called slices

  which are assigned to clients. Clients can query the slice details, activate

  and deactivate them.



properties:

  compatible:

    enum:

      - qcom,sc7180-llcc

      - qcom,sdm845-llcc



  reg:

    items:

      - description: LLCC base register region

      - description: LLCC broadcast base register region



  reg-names:

    items:

      - const: llcc_base

      - const: llcc_broadcast_base



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg

  - reg-names

  - interrupts



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    cache-controller@1100000 {

      compatible = "qcom,sdm845-llcc";

      reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;

      reg-names = "llcc_base", "llcc_broadcast_base";

      interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;

    };

Documentation/devicetree/bindings/arm/omap/prm-inst.txt

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OMAP PRM instance bindings



Power and Reset Manager is an IP block on OMAP family of devices which

handle the power domains and their current state, and provide reset

handling for the domains and/or separate IP blocks under the power domain

hierarchy.



Required properties:

- compatible:	Must contain one of the following:

		"ti,am3-prm-inst"

		"ti,am4-prm-inst"

		"ti,omap4-prm-inst"

		"ti,omap5-prm-inst"

		"ti,dra7-prm-inst"

		and additionally must contain:

		"ti,omap-prm-inst"

- reg:		Contains PRM instance register address range

		(base address and length)



Optional properties:

- #reset-cells:	Should be 1 if the PRM instance in question supports resets.



Example:



prm_dsp2: prm@1b00 {

	compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";

	reg = <0x1b00 0x40>;

	#reset-cells = <1>;

};

Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt

+15 −1
Original line number Diff line number Diff line
@@ -11,7 +11,9 @@ power management service, FPGA service and other platform management 
services.



Required properties:

 - compatible:	Must contain:	"xlnx,zynqmp-firmware"

 - compatible:	Must contain any of below:

		"xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC

		"xlnx,versal-firmware" for Versal

 - method:	The method of calling the PM-API firmware layer.

		Permitted values are:

		  - "smc" : SMC #0, following the SMCCC
@@ -21,6 +23,8 @@ Required properties: 
Example

-------



Zynq Ultrascale+ MPSoC

----------------------

firmware {

	zynqmp_firmware: zynqmp-firmware {

		compatible = "xlnx,zynqmp-firmware";
@@ -28,3 +32,13 @@ firmware { 
		...

	};

};



Versal

------

firmware {

	versal_firmware: versal-firmware {

		compatible = "xlnx,versal-firmware";

		method = "smc";

		...

	};

};

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