Commit ec7b3f53 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-fix-v5.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi fixes from Mark Brown:
 "A small collection of fixes here, one to make the newly added PTP
  timestamping code more accurate, a few driver fixes and a fix for the
  core DT binding to document the fact that we support eight wire buses"

* tag 'spi-fix-v5.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
  spi: Document Octal mode as valid SPI bus width
  spi: spi-dw: Add lock protect dw_spi rx/tx to prevent concurrent calls
  spi: spi-fsl-dspi: Fix 16-bit word order in 32-bit XSPI mode
  spi: Don't look at TX buffer for PTP system timestamping
  spi: uniphier: Fix FIFO threshold
parents 5acefdc2 09b6636c

Documentation/devicetree/bindings/spi/spi-controller.yaml

+2 −2
Original line number Diff line number Diff line
@@ -111,7 +111,7 @@ patternProperties: 
      spi-rx-bus-width:

        allOf:

          - $ref: /schemas/types.yaml#/definitions/uint32

          - enum: [ 1, 2, 4 ]

          - enum: [ 1, 2, 4, 8 ]

          - default: 1

        description:

          Bus width to the SPI bus used for MISO.
@@ -123,7 +123,7 @@ patternProperties: 
      spi-tx-bus-width:

        allOf:

          - $ref: /schemas/types.yaml#/definitions/uint32

          - enum: [ 1, 2, 4 ]

          - enum: [ 1, 2, 4, 8 ]

          - default: 1

        description:

          Bus width to the SPI bus used for MOSI.

drivers/spi/spi-dw.c

+12 −3
Original line number Diff line number Diff line
@@ -172,9 +172,11 @@ static inline u32 rx_max(struct dw_spi *dws) 


static void dw_writer(struct dw_spi *dws)

{

	u32 max = tx_max(dws);

	u32 max;

	u16 txw = 0;



	spin_lock(&dws->buf_lock);

	max = tx_max(dws);

	while (max--) {

		/* Set the tx word if the transfer's original "tx" is not null */

		if (dws->tx_end - dws->len) {
@@ -186,13 +188,16 @@ static void dw_writer(struct dw_spi *dws) 
		dw_write_io_reg(dws, DW_SPI_DR, txw);

		dws->tx += dws->n_bytes;

	}

	spin_unlock(&dws->buf_lock);

}



static void dw_reader(struct dw_spi *dws)

{

	u32 max = rx_max(dws);

	u32 max;

	u16 rxw;



	spin_lock(&dws->buf_lock);

	max = rx_max(dws);

	while (max--) {

		rxw = dw_read_io_reg(dws, DW_SPI_DR);

		/* Care rx only if the transfer's original "rx" is not null */
@@ -204,6 +209,7 @@ static void dw_reader(struct dw_spi *dws) 
		}

		dws->rx += dws->n_bytes;

	}

	spin_unlock(&dws->buf_lock);

}



static void int_error_stop(struct dw_spi *dws, const char *msg)
@@ -276,18 +282,20 @@ static int dw_spi_transfer_one(struct spi_controller *master, 
{

	struct dw_spi *dws = spi_controller_get_devdata(master);

	struct chip_data *chip = spi_get_ctldata(spi);

	unsigned long flags;

	u8 imask = 0;

	u16 txlevel = 0;

	u32 cr0;

	int ret;



	dws->dma_mapped = 0;



	spin_lock_irqsave(&dws->buf_lock, flags);

	dws->tx = (void *)transfer->tx_buf;

	dws->tx_end = dws->tx + transfer->len;

	dws->rx = transfer->rx_buf;

	dws->rx_end = dws->rx + transfer->len;

	dws->len = transfer->len;

	spin_unlock_irqrestore(&dws->buf_lock, flags);



	spi_enable_chip(dws, 0);
@@ -471,6 +479,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) 
	dws->type = SSI_MOTO_SPI;

	dws->dma_inited = 0;

	dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);

	spin_lock_init(&dws->buf_lock);



	spi_controller_set_devdata(master, dws);

drivers/spi/spi-dw.h

+1 −0
Original line number Diff line number Diff line
@@ -119,6 +119,7 @@ struct dw_spi { 
	size_t			len;

	void			*tx;

	void			*tx_end;

	spinlock_t		buf_lock;

	void			*rx;

	void			*rx_end;

	int			dma_mapped;

drivers/spi/spi-fsl-dspi.c

+10 −14
Original line number Diff line number Diff line
@@ -185,6 +185,7 @@ struct fsl_dspi { 
	struct spi_transfer			*cur_transfer;

	struct spi_message			*cur_msg;

	struct chip_data			*cur_chip;

	size_t					progress;

	size_t					len;

	const void				*tx;

	void					*rx;
@@ -586,21 +587,14 @@ static void dspi_tcfq_write(struct fsl_dspi *dspi) 
	dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;



	if (dspi->devtype_data->xspi_mode && dspi->bits_per_word > 16) {

		/* Write two TX FIFO entries first, and then the corresponding

		 * CMD FIFO entry.

		/* Write the CMD FIFO entry first, and then the two

		 * corresponding TX FIFO entries.

		 */

		u32 data = dspi_pop_tx(dspi);



		if (dspi->cur_chip->ctar_val & SPI_CTAR_LSBFE) {

			/* LSB */

		cmd_fifo_write(dspi);

		tx_fifo_write(dspi, data & 0xFFFF);

		tx_fifo_write(dspi, data >> 16);

		} else {

			/* MSB */

			tx_fifo_write(dspi, data >> 16);

			tx_fifo_write(dspi, data & 0xFFFF);

		}

		cmd_fifo_write(dspi);

	} else {

		/* Write one entry to both TX FIFO and CMD FIFO

		 * simultaneously.
@@ -658,7 +652,7 @@ static int dspi_rxtx(struct fsl_dspi *dspi) 
	u32 spi_tcr;



	spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer,

				dspi->tx - dspi->bytes_per_word, !dspi->irq);

				dspi->progress, !dspi->irq);



	/* Get transfer counter (in number of SPI transfers). It was

	 * reset to 0 when transfer(s) were started.
@@ -667,6 +661,7 @@ static int dspi_rxtx(struct fsl_dspi *dspi) 
	spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);

	/* Update total number of bytes that were transferred */

	msg->actual_length += spi_tcnt * dspi->bytes_per_word;

	dspi->progress += spi_tcnt;



	trans_mode = dspi->devtype_data->trans_mode;

	if (trans_mode == DSPI_EOQ_MODE)
@@ -679,7 +674,7 @@ static int dspi_rxtx(struct fsl_dspi *dspi) 
		return 0;



	spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,

			       dspi->tx, !dspi->irq);

			       dspi->progress, !dspi->irq);



	if (trans_mode == DSPI_EOQ_MODE)

		dspi_eoq_write(dspi);
@@ -768,6 +763,7 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, 
		dspi->rx = transfer->rx_buf;

		dspi->rx_end = dspi->rx + transfer->len;

		dspi->len = transfer->len;

		dspi->progress = 0;

		/* Validated transfer specific frame size (defaults applied) */

		dspi->bits_per_word = transfer->bits_per_word;

		if (transfer->bits_per_word <= 8)
@@ -789,7 +785,7 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, 
				     SPI_CTARE_DTCP(1));



		spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,

				       dspi->tx, !dspi->irq);

				       dspi->progress, !dspi->irq);



		trans_mode = dspi->devtype_data->trans_mode;

		switch (trans_mode) {

drivers/spi/spi-uniphier.c

+19 −12
Original line number Diff line number Diff line
@@ -290,25 +290,32 @@ static void uniphier_spi_recv(struct uniphier_spi_priv *priv) 
	}

}



static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv)

static void uniphier_spi_set_fifo_threshold(struct uniphier_spi_priv *priv,

					    unsigned int threshold)

{

	unsigned int fifo_threshold, fill_bytes;

	u32 val;



	fifo_threshold = DIV_ROUND_UP(priv->rx_bytes,

				bytes_per_word(priv->bits_per_word));

	fifo_threshold = min(fifo_threshold, SSI_FIFO_DEPTH);



	fill_bytes = fifo_threshold - (priv->rx_bytes - priv->tx_bytes);



	/* set fifo threshold */

	val = readl(priv->base + SSI_FC);

	val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK);

	val |= FIELD_PREP(SSI_FC_TXFTH_MASK, fifo_threshold);

	val |= FIELD_PREP(SSI_FC_RXFTH_MASK, fifo_threshold);

	val |= FIELD_PREP(SSI_FC_TXFTH_MASK, SSI_FIFO_DEPTH - threshold);

	val |= FIELD_PREP(SSI_FC_RXFTH_MASK, threshold);

	writel(val, priv->base + SSI_FC);

}



static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv)

{

	unsigned int fifo_threshold, fill_words;

	unsigned int bpw = bytes_per_word(priv->bits_per_word);



	fifo_threshold = DIV_ROUND_UP(priv->rx_bytes, bpw);

	fifo_threshold = min(fifo_threshold, SSI_FIFO_DEPTH);



	uniphier_spi_set_fifo_threshold(priv, fifo_threshold);



	fill_words = fifo_threshold -

		DIV_ROUND_UP(priv->rx_bytes - priv->tx_bytes, bpw);



	while (fill_bytes--)

	while (fill_words--)

		uniphier_spi_send(priv);

}

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