Commit ec6f5e0e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-urgent-2020-12-13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 fixes from Thomas Gleixner:
 "A set of x86 and membarrier fixes:

   - Correct a few problems in the x86 and the generic membarrier
     implementation. Small corrections for assumptions about visibility
     which have turned out not to be true.

   - Make the PAT bits for memory encryption correct vs 4K and 2M/1G
     page table entries as they are at a different location.

   - Fix a concurrency issue in the the local bandwidth readout of
     resource control leading to incorrect values

   - Fix the ordering of allocating a vector for an interrupt. The order
     missed to respect the provided cpumask when the first attempt of
     allocating node local in the mask fails. It then tries the node
     instead of trying the full provided mask first. This leads to
     erroneous error messages and breaking the (user) supplied affinity
     request. Reorder it.

   - Make the INT3 padding detection in optprobe work correctly"

* tag 'x86-urgent-2020-12-13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/kprobes: Fix optprobe to detect INT3 padding correctly
  x86/apic/vector: Fix ordering in vector assignment
  x86/resctrl: Fix incorrect local bandwidth when mba_sc is enabled
  x86/mm/mem_encrypt: Fix definition of PMD_FLAGS_DEC_WP
  membarrier: Execute SYNC_CORE on the calling thread
  membarrier: Explicitly sync remote cores when SYNC_CORE is requested
  membarrier: Add an actual barrier before rseq_preempt()
  x86/membarrier: Get rid of a dubious optimization
parents d2360a39 0d07c0ec

arch/x86/include/asm/pgtable_types.h

+1 −0
Original line number Diff line number Diff line
@@ -155,6 +155,7 @@ enum page_cache_mode { 
#define _PAGE_ENC		(_AT(pteval_t, sme_me_mask))



#define _PAGE_CACHE_MASK	(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)

#define _PAGE_LARGE_CACHE_MASK	(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT_LARGE)



#define _PAGE_NOCACHE		(cachemode2protval(_PAGE_CACHE_MODE_UC))

#define _PAGE_CACHE_WP		(cachemode2protval(_PAGE_CACHE_MODE_WP))

arch/x86/include/asm/sync_core.h

+5 −4
Original line number Diff line number Diff line
@@ -98,12 +98,13 @@ static inline void sync_core_before_usermode(void) 
	/* With PTI, we unconditionally serialize before running user code. */

	if (static_cpu_has(X86_FEATURE_PTI))

		return;



	/*

	 * Return from interrupt and NMI is done through iret, which is core

	 * serializing.

	 * Even if we're in an interrupt, we might reschedule before returning,

	 * in which case we could switch to a different thread in the same mm

	 * and return using SYSRET or SYSEXIT.  Instead of trying to keep

	 * track of our need to sync the core, just sync right away.

	 */

	if (in_irq() || in_nmi())

		return;

	sync_core();

}

arch/x86/kernel/apic/vector.c

+14 −10
Original line number Diff line number Diff line
@@ -273,20 +273,24 @@ static int assign_irq_vector_any_locked(struct irq_data *irqd) 
	const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);

	int node = irq_data_get_node(irqd);



	if (node == NUMA_NO_NODE)

		goto all;

	if (node != NUMA_NO_NODE) {

		/* Try the intersection of @affmsk and node mask */

		cpumask_and(vector_searchmask, cpumask_of_node(node), affmsk);

		if (!assign_vector_locked(irqd, vector_searchmask))

			return 0;

	/* Try the node mask */

	if (!assign_vector_locked(irqd, cpumask_of_node(node)))

		return 0;

all:

	}



	/* Try the full affinity mask */

	cpumask_and(vector_searchmask, affmsk, cpu_online_mask);

	if (!assign_vector_locked(irqd, vector_searchmask))

		return 0;



	if (node != NUMA_NO_NODE) {

		/* Try the node mask */

		if (!assign_vector_locked(irqd, cpumask_of_node(node)))

			return 0;

	}



	/* Try the full online mask */

	return assign_vector_locked(irqd, cpu_online_mask);

}

arch/x86/kernel/cpu/resctrl/monitor.c

+2 −4
Original line number Diff line number Diff line
@@ -279,7 +279,6 @@ static void mbm_bw_count(u32 rmid, struct rmid_read *rr) 
		return;



	chunks = mbm_overflow_count(m->prev_bw_msr, tval, rr->r->mbm_width);

	m->chunks += chunks;

	cur_bw = (chunks * r->mon_scale) >> 20;



	if (m->delta_comp)
@@ -450,15 +449,14 @@ static void mbm_update(struct rdt_resource *r, struct rdt_domain *d, int rmid) 
	}

	if (is_mbm_local_enabled()) {

		rr.evtid = QOS_L3_MBM_LOCAL_EVENT_ID;

		__mon_event_count(rmid, &rr);



		/*

		 * Call the MBA software controller only for the

		 * control groups and when user has enabled

		 * the software controller explicitly.

		 */

		if (!is_mba_sc(NULL))

			__mon_event_count(rmid, &rr);

		else

		if (is_mba_sc(NULL))

			mbm_bw_count(rmid, &rr);

	}

}

arch/x86/kernel/kprobes/opt.c

+20 −2
Original line number Diff line number Diff line
@@ -272,6 +272,19 @@ static int insn_is_indirect_jump(struct insn *insn) 
	return ret;

}



static bool is_padding_int3(unsigned long addr, unsigned long eaddr)

{

	unsigned char ops;



	for (; addr < eaddr; addr++) {

		if (get_kernel_nofault(ops, (void *)addr) < 0 ||

		    ops != INT3_INSN_OPCODE)

			return false;

	}



	return true;

}



/* Decode whole function to ensure any instructions don't jump into target */

static int can_optimize(unsigned long paddr)

{
@@ -310,9 +323,14 @@ static int can_optimize(unsigned long paddr) 
			return 0;

		kernel_insn_init(&insn, (void *)recovered_insn, MAX_INSN_SIZE);

		insn_get_length(&insn);

		/* Another subsystem puts a breakpoint */

		/*

		 * In the case of detecting unknown breakpoint, this could be

		 * a padding INT3 between functions. Let's check that all the

		 * rest of the bytes are also INT3.

		 */

		if (insn.opcode.bytes[0] == INT3_INSN_OPCODE)

			return 0;

			return is_padding_int3(addr, paddr - offset + size) ? 1 : 0;



		/* Recover address */

		insn.kaddr = (void *)addr;

		insn.next_byte = (void *)(addr + insn.length);

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