Commit ec481536 authored by H. Peter Anvin's avatar H. Peter Anvin Committed by Linus Torvalds
Browse files

Unify the CPU features vectors between i386 and x86-64 



Unify the handling of the CPU features vectors between i386 and x86-64.
This also adopts the collapsing of features which are required at
compile-time into constant tests from x86-64 to i386.

Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent f8c09377

arch/i386/kernel/cpu/proc.c

+9 −6
Original line number Diff line number Diff line
@@ -29,7 +29,8 @@ static int show_cpuinfo(struct seq_file *m, void *v) 
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, "mp", "nx", NULL, "mmxext", NULL,

		NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm", "3dnowext", "3dnow",

		NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",

		"3dnowext", "3dnow",



		/* Transmeta-defined */

		"recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
@@ -40,8 +41,9 @@ static int show_cpuinfo(struct seq_file *m, void *v) 
		/* Other (Linux-defined) */

		"cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",

		NULL, NULL, NULL, NULL,

		"constant_tsc", "up", NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		"constant_tsc", "up", NULL, "arch_perfmon",

		"pebs", "bts", NULL, "sync_rdtsc",

		"rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,



		/* Intel-defined (#2) */
@@ -57,9 +59,10 @@ static int show_cpuinfo(struct seq_file *m, void *v) 
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,



		/* AMD-defined (#2) */

		"lahf_lm", "cmp_legacy", "svm", "extapic", "cr8legacy", "abm",

		"sse4a", "misalignsse",

		"3dnowprefetch", "osvw", "ibs", NULL, NULL, NULL, NULL, NULL,

		"lahf_lm", "cmp_legacy", "svm", "extapic", "cr8_legacy",

		"altmovcr8", "abm", "sse4a",

		"misalignsse", "3dnowprefetch",

		"osvw", "ibs", NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

	};

arch/i386/kernel/verify_cpu.S

+6 −6
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ verify_cpu: 
	testl	$(1<<18),%eax

	jz	bad

#endif

#if REQUIRED_MASK1 != 0

#if REQUIRED_MASK0 != 0

	pushfl				# standard way to check for cpuid

	popl	%eax

	movl	%eax,%ebx
@@ -39,14 +39,14 @@ verify_cpu: 
	pushfl

	popl	%eax

	cmpl	%eax,%ebx

	jz	bad			# REQUIRED_MASK1 != 0 requires CPUID

	jz	bad			# REQUIRED_MASK0 != 0 requires CPUID



	movl	$0x0,%eax		# See if cpuid 1 is implemented

	cpuid

	cmpl	$0x1,%eax

	jb	bad			# no cpuid 1



#if REQUIRED_MASK1 & NEED_CMPXCHG64

#if REQUIRED_MASK0 & NEED_CMPXCHG64

	/* Some VIA C3s need magic MSRs to enable CX64. Do this here */

	cmpl	$0x746e6543,%ebx	# Cent

	jne	1f
@@ -79,10 +79,10 @@ verify_cpu: 
#error	add proper model checking here

#endif



	andl	$REQUIRED_MASK1,%edx

	xorl	$REQUIRED_MASK1,%edx

	andl	$REQUIRED_MASK0,%edx

	xorl	$REQUIRED_MASK0,%edx

	jnz	bad

#endif /* REQUIRED_MASK1 */

#endif /* REQUIRED_MASK0 */



	popfl

	xor	%eax,%eax

arch/x86_64/kernel/setup.c

+7 −6
Original line number Diff line number Diff line
@@ -931,7 +931,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) 
	        "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",

	        "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",

	        "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",

	        "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,

	        "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",



		/* AMD-defined */

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -947,10 +947,11 @@ static int show_cpuinfo(struct seq_file *m, void *v) 
		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,



		/* Other (Linux-defined) */

		"cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,

		"constant_tsc", NULL, NULL,

		"up", NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		"cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",

		NULL, NULL, NULL, NULL,

		"constant_tsc", "up", NULL, "arch_perfmon",

		"pebs", "bts", NULL, "sync_rdtsc",

		"rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,



		/* Intel-defined (#2) */
@@ -961,7 +962,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) 


		/* VIA/Cyrix/Centaur-defined */

		NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		"ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

		NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

arch/x86_64/kernel/verify_cpu.S

+4 −18
Original line number Diff line number Diff line
@@ -37,20 +37,6 @@ verify_cpu: 
	pushl	$0			# Kill any dangerous flags

	popfl



	/* minimum CPUID flags for x86-64 as defined by AMD */

#define M(x) (1<<(x))

#define M2(a,b) M(a)|M(b)

#define M4(a,b,c,d) M(a)|M(b)|M(c)|M(d)



#define SSE_MASK \

	(M2(X86_FEATURE_XMM,X86_FEATURE_XMM2))

#define REQUIRED_MASK1 \

	(M4(X86_FEATURE_FPU,X86_FEATURE_PSE,X86_FEATURE_TSC,X86_FEATURE_MSR)|\

	 M4(X86_FEATURE_PAE,X86_FEATURE_CX8,X86_FEATURE_PGE,X86_FEATURE_CMOV)|\

	 M(X86_FEATURE_FXSR))

#define REQUIRED_MASK2 \

	(M(X86_FEATURE_LM - 32))



	pushfl				# standard way to check for cpuid

	popl	%eax

	movl	%eax,%ebx
@@ -79,8 +65,8 @@ verify_cpu: 
verify_cpu_noamd:

	movl    $0x1,%eax		# Does the cpu have what it takes

	cpuid

	andl	$REQUIRED_MASK1,%edx

	xorl	$REQUIRED_MASK1,%edx

	andl	$REQUIRED_MASK0,%edx

	xorl	$REQUIRED_MASK0,%edx

	jnz	verify_cpu_no_longmode



	movl    $0x80000000,%eax	# See if extended cpuid is implemented
@@ -90,8 +76,8 @@ verify_cpu_noamd: 


	movl    $0x80000001,%eax	# Does the cpu have what it takes

	cpuid

	andl    $REQUIRED_MASK2,%edx

	xorl    $REQUIRED_MASK2,%edx

	andl    $REQUIRED_MASK1,%edx

	xorl    $REQUIRED_MASK1,%edx

	jnz     verify_cpu_no_longmode



verify_cpu_sse_test:

include/asm-i386/cpufeature.h

+12 −5
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ 
#define X86_FEATURE_BTS		(3*32+13)  /* Branch Trace Store */

#define X86_FEATURE_LAPIC_TIMER_BROKEN (3*32+ 14) /* lapic timer broken in C1 */

#define X86_FEATURE_SYNC_RDTSC	(3*32+15)  /* RDTSC synchronizes the CPU */

#define X86_FEATURE_REP_GOOD   (3*32+16) /* rep microcode works well on this CPU */



/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */

#define X86_FEATURE_XMM3	(4*32+ 0) /* Streaming SIMD Extensions-3 */
@@ -109,9 +110,15 @@ 
#define X86_FEATURE_CMP_LEGACY	(6*32+ 1) /* If yes HyperThreading not valid */



#define cpu_has(c, bit)							\

	((__builtin_constant_p(bit) && (bit) < 32 && 	\

		(1UL << (bit)) & REQUIRED_MASK1) ?	\

		1 : 					\

	(__builtin_constant_p(bit) &&					\

	 ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) ||	\

	   (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) ||	\

	   (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) ||	\

	   (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) ||	\

	   (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) ||	\

	   (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) ||	\

	   (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) )	\

	  ? 1 :								\

	  test_bit(bit, (c)->x86_capability))

#define boot_cpu_has(bit)	cpu_has(&boot_cpu_data, bit)

CRA Git | Maintained and supported by SUSTech CRA and CCSE