Commit ec4401d3 authored May 21, 2019 by Gwan-gyeong Mun Committed by Jani Nikula May 23, 2019

drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA



When YCBCR 4:2:0 outputs is used for DP, we should program YCBCR 4:2:0 to
MSA and VSC SDP.

As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication of Color
Encoding Format and Content Color Gamut] while sending YCBCR 420 signals
we should program MSA MISC1 fields which indicate VSC SDP for the Pixel
Encoding/Colorimetry Format.

v2: Block comment style fix.

v6:
  Fix an wrong setting of MSA MISC1 fields for Pixel Encoding/Colorimetry
  Format indication. As per DP 1.4a spec Table 2-96 [MSA MISC1 and MISC0
  Fields for Pixel Encoding/Colorimetry Format Indication]
  When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to
  indicate the Pixel Encoding/Colorimetry Format. On the wrong version
  it set a bit 5 of MISC1, now it set a bit 6 of MISC1.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190521121721.32010-5-gwan-gyeong.mun@intel.com

parent 3c053a96

drivers/gpu/drm/i915/i915_reg.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -9527,6 +9527,7 @@ enum skl_power_gate {
		#define TRANS_MSA_12_BPC (3 << 5)
		#define TRANS_MSA_16_BPC (4 << 5)
		#define TRANS_MSA_CEA_RANGE (1 << 3)
		#define TRANS_MSA_USE_VSC_SDP (1 << 14)

		/* LCPLL Control */
		#define LCPLL_CTL _MMIO(0x130040)

drivers/gpu/drm/i915/intel_ddi.c

+8 −0

Original line number	Diff line number	Diff line
		@@ -1717,6 +1717,14 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
		*/
		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
		temp \|= TRANS_MSA_SAMPLING_444 \| TRANS_MSA_CLRSP_YCBCR;
		/*
		* As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
		* of Color Encoding Format and Content Color Gamut] while sending
		* YCBCR 420 signals we should program MSA MISC1 fields which
		* indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
		*/
		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
		temp \|= TRANS_MSA_USE_VSC_SDP;
		I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
		}

Admin message