Commit ec38fad3 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-arm64-dt2-for-v5.1' of... 

Merge tag 'renesas-arm64-dt2-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/dt

Second Round of Renesas ARM64 Based SoC DT Updates for v5.1

* R-Car Gen3 SoC based Salvator-X, Salvator-XS and ULCB boards
  - Enable HS400 support for eMMC

* R-Car E3 (r7a77990) SoC
  - Add OPPs table for cpu devices

* RZ/G2E (r8a774c0) SoC
  - Describe TMU, CMT, SDHI devices in DT
  - Describe pincontrol support for SCIF2 device in DT
  - Add OPPs table for cpu devices

* RZ/G2E (r8a774c0) based EK874 board and CAT875 sub-board,
  and CAT874 board
  - Initial support

* tag 'renesas-arm64-dt2-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

:
  arm64: dts: renesas: cat875: Enable PCIe support
  arm64: dts: renesas: r8a774c0-cat874: Add pciec0 support
  arm64: dts: renesas: r8a774c0: Add TMU device nodes
  arm64: dts: renesas: r8a774c0: Add CMT device nodes
  arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices
  arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices
  arm64: dts: renesas: enable HS400 on R-Car Gen3
  arm64: dts: renesas: cat875: Add ethernet support
  arm64: dts: renesas: r8a774c0-cat874: Add uSD support
  arm64: dts: renesas: r8a774c0-cat874: Add pincontrol support to scif2
  arm64: dts: renesas: Add Si-Linux EK874 board support
  arm64: dts: renesas: Add Si-Linux CAT874 board support

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents d0bc1883 ee20aeef

arch/arm64/boot/dts/renesas/Makefile

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# SPDX-License-Identifier: GPL-2.0

dtb-$(CONFIG_ARCH_R8A774C0) += r8a774c0-cat874.dtb r8a774c0-ek874.dtb

dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb

dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-h3ulcb-kf.dtb

dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb

arch/arm64/boot/dts/renesas/cat875.dtsi

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// SPDX-License-Identifier: GPL-2.0

/*

 * Device Tree Source for the Silicon Linux sub board for CAT874 (CAT875)

 *

 * Copyright (C) 2019 Renesas Electronics Corp.

 */



/ {

	model = "Silicon Linux sub board for CAT874 (CAT875)";



	aliases {

		ethernet0 = &avb;

	};

};



&avb {

	pinctrl-0 = <&avb_pins>;

	pinctrl-names = "default";

	renesas,no-ether-link;

	phy-handle = <&phy0>;

	phy-mode = "rgmii";

	status = "okay";



	phy0: ethernet-phy@0 {

		rxc-skew-ps = <1500>;

		reg = <0>;

		interrupt-parent = <&gpio2>;

		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;

		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;

	};

};



&pciec0 {

	status = "okay";

};



&pfc {

	avb_pins: avb {

		mux {

			groups = "avb_mii";

			function = "avb";

		};

	};

};

arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts

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// SPDX-License-Identifier: GPL-2.0

/*

 * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874)

 *

 * Copyright (C) 2019 Renesas Electronics Corp.

 */



/dts-v1/;

#include "r8a774c0.dtsi"

#include <dt-bindings/gpio/gpio.h>



/ {

	model = "Silicon Linux RZ/G2E 96board platform (CAT874)";

	compatible = "si-linux,cat874", "renesas,r8a774c0";



	aliases {

		serial0 = &scif2;

	};



	chosen {

		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";

		stdout-path = "serial0:115200n8";

	};



	memory@48000000 {

		device_type = "memory";

		/* first 128MB is reserved for secure area. */

		reg = <0x0 0x48000000 0x0 0x78000000>;

	};



	vcc_sdhi0: regulator-vcc-sdhi0 {

		compatible = "regulator-fixed";



		regulator-name = "SDHI0 Vcc";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		regulator-always-on;

		regulator-boot-on;

	};



	vccq_sdhi0: regulator-vccq-sdhi0 {

		compatible = "regulator-gpio";



		regulator-name = "SDHI0 VccQ";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <3300000>;



		gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;

		gpios-states = <1>;

		states = <3300000 1

			  1800000 0>;

	};

};



&extal_clk {

	clock-frequency = <48000000>;

};



&pcie_bus_clk {

	clock-frequency = <100000000>;

};



&pciec0 {

	/* Map all possible DDR as inbound ranges */

	dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

};



&pfc {

	scif2_pins: scif2 {

		groups = "scif2_data_a";

		function = "scif2";

	};



	sdhi0_pins: sd0 {

		groups = "sdhi0_data4", "sdhi0_ctrl";

		function = "sdhi0";

		power-source = <3300>;

	};



	sdhi0_pins_uhs: sd0_uhs {

		groups = "sdhi0_data4", "sdhi0_ctrl";

		function = "sdhi0";

		power-source = <1800>;

	};

};



&scif2 {

	pinctrl-0 = <&scif2_pins>;

	pinctrl-names = "default";



	status = "okay";

};



&sdhi0 {

	pinctrl-0 = <&sdhi0_pins>;

	pinctrl-1 = <&sdhi0_pins_uhs>;

	pinctrl-names = "default", "state_uhs";



	vmmc-supply = <&vcc_sdhi0>;

	vqmmc-supply = <&vccq_sdhi0>;

	cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;

	bus-width = <4>;

	sd-uhs-sdr50;

	sd-uhs-sdr104;

	status = "okay";

};

arch/arm64/boot/dts/renesas/r8a774c0-ek874.dts

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// SPDX-License-Identifier: GPL-2.0

/*

 * Device Tree Source for the Silicon Linux RZ/G2E evaluation kit (EK874)

 *

 * Copyright (C) 2019 Renesas Electronics Corp.

 */



#include "r8a774c0-cat874.dts"

#include "cat875.dtsi"



/ {

	model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875)";

	compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";

};

arch/arm64/boot/dts/renesas/r8a774c0.dtsi

+160 −0
Original line number Diff line number Diff line
@@ -44,6 +44,27 @@ 
		clock-frequency = <0>;

	};



	cluster1_opp: opp_table10 {

		compatible = "operating-points-v2";

		opp-shared;

		opp-800000000 {

			opp-hz = /bits/ 64 <800000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

		};

		opp-1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

		};

		opp-1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

			opp-suspend;

		};

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -55,6 +76,8 @@ 
			power-domains = <&sysc R8A774C0_PD_CA53_CPU0>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		a53_1: cpu@1 {
@@ -64,6 +87,8 @@ 
			power-domains = <&sysc R8A774C0_PD_CA53_CPU1>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A774C0_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		L2_CA53: cache-controller-0 {
@@ -234,6 +259,76 @@ 
			reg = <0 0xe6060000 0 0x508>;

		};



		cmt0: timer@e60f0000 {

			compatible = "renesas,r8a774c0-cmt0",

				     "renesas,rcar-gen3-cmt0";

			reg = <0 0xe60f0000 0 0x1004>;

			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 303>;

			clock-names = "fck";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 303>;

			status = "disabled";

		};



		cmt1: timer@e6130000 {

			compatible = "renesas,r8a774c0-cmt1",

				     "renesas,rcar-gen3-cmt1";

			reg = <0 0xe6130000 0 0x1004>;

			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 302>;

			clock-names = "fck";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 302>;

			status = "disabled";

		};



		cmt2: timer@e6140000 {

			compatible = "renesas,r8a774c0-cmt1",

				     "renesas,rcar-gen3-cmt1";

			reg = <0 0xe6140000 0 0x1004>;

			interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 301>;

			clock-names = "fck";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 301>;

			status = "disabled";

		};



		cmt3: timer@e6148000 {

			compatible = "renesas,r8a774c0-cmt1",

				     "renesas,rcar-gen3-cmt1";

			reg = <0 0xe6148000 0 0x1004>;

			interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 300>;

			clock-names = "fck";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 300>;

			status = "disabled";

		};



		cpg: clock-controller@e6150000 {

			compatible = "renesas,r8a774c0-cpg-mssr";

			reg = <0 0xe6150000 0 0x1000>;
@@ -283,6 +378,71 @@ 
			resets = <&cpg 407>;

		};



		tmu0: timer@e61e0000 {

			compatible = "renesas,tmu-r8a774c0", "renesas,tmu";

			reg = <0 0xe61e0000 0 0x30>;

			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 125>;

			clock-names = "fck";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 125>;

			status = "disabled";

		};



		tmu1: timer@e6fc0000 {

			compatible = "renesas,tmu-r8a774c0", "renesas,tmu";

			reg = <0 0xe6fc0000 0 0x30>;

			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 124>;

			clock-names = "fck";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 124>;

			status = "disabled";

		};



		tmu2: timer@e6fd0000 {

			compatible = "renesas,tmu-r8a774c0", "renesas,tmu";

			reg = <0 0xe6fd0000 0 0x30>;

			interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 123>;

			clock-names = "fck";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 123>;

			status = "disabled";

		};



		tmu3: timer@e6fe0000 {

			compatible = "renesas,tmu-r8a774c0", "renesas,tmu";

			reg = <0 0xe6fe0000 0 0x30>;

			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 122>;

			clock-names = "fck";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 122>;

			status = "disabled";

		};



		tmu4: timer@ffc00000 {

			compatible = "renesas,tmu-r8a774c0", "renesas,tmu";

			reg = <0 0xffc00000 0 0x30>;

			interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 121>;

			clock-names = "fck";

			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;

			resets = <&cpg 121>;

			status = "disabled";

		};



		i2c0: i2c@e6500000 {

			#address-cells = <1>;

			#size-cells = <0>;

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