Commit ec22ab00 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'macsec-hw-offload' 

Antoine Tenart says:

====================
net: macsec: initial support for hardware offloading

This series intends to add support for offloading MACsec transformations
to hardware enabled devices. The series adds the necessary
infrastructure for offloading MACsec configurations to hardware drivers,
in patches 1 to 5; then introduces MACsec offloading support in the
Microsemi MSCC PHY driver, in patches 6 to 10.

The series can also be found at:
https://github.com/atenart/linux/tree/net-next/macsec

IProute2 modifications can be found at:
https://github.com/atenart/iproute2/tree/macsec



MACsec hardware offloading infrastructure
-----------------------------------------

Linux has a software implementation of the MACsec standard. There are
hardware engines supporting MACsec operations, such as the Intel ixgbe
NIC and some Microsemi PHYs (the one we use in this series). This means
the MACsec offloading infrastructure should support networking PHY and
MAC drivers. Note that MAC driver preliminary support is part of this
series, but should not be merged before we actually have a provider for
this.

We do intend in this series to re-use the logic, netlink API and data
structures of the existing MACsec software implementation. This allows
not to duplicate definitions and structure storing the same information;
as well as using the same userspace tools to configure both software or
hardware offloaded MACsec flows (with `ip macsec`).

When adding a new MACsec virtual interface the existing logic is kept:
offloading is disabled by default. A user driven configuration choice is
needed to switch to offloading mode (a patch in iproute2 is needed for
this). A single MACsec interface can be offloaded for now, and some
limitations are there: no flow can be moved from one implementation to
the other so the decision needs to be done before configuring the
interface.

MACsec offloading ops are called in 2 steps: a preparation one, and a
commit one. The first step is allowed to fail and should be used to
check if a provided configuration is compatible with a given MACsec
capable hardware. The second step is not allowed to fail and should
only be used to enable a given MACsec configuration.

A limitation as of now is the counters and statistics are not reported
back from the hardware to the software MACsec implementation. This
isn't an issue when using offloaded MACsec transformations, but it
should be added in the future so that the MACsec state can be reported
to the user (which would also improve the debug).

Microsemi PHY MACsec support
----------------------------

In order to add support for the MACsec offloading feature in the
Microsemi MSCC PHY driver, the __phy_read_page and __phy_write_page
helpers had to be exported. This is because the initialization of the
PHY is done while holding the MDIO bus lock, and we need to change the
page to configure the MACsec block.

The support itself is then added in three patches. The first one adds
support for configuring the MACsec block within the PHY, so that it is
up, running and available for future configuration, but is not doing any
modification on the traffic passing through the PHY. The second patch
implements the phy_device MACsec ops in the Microsemi MSCC PHY driver,
and introduce helpers to configure MACsec transformations and flows to
match specific packets. The last one adds support for PN rollover.

Thanks!
Antoine

Since v5:
  - Fixed a compilation issue due to an inclusion from an UAPI header.
  - Added an EXPORT_SYMBOL_GPL for the PN rollover helper, to fix module
    compilation issues.
  - Added a dependency for the MSCC driver on MACSEC || MACSEC=n.
  - Removed the patches including the MAC offloading support as they are
    not to be applied for now.

Since v4:
  - Reworked the MACsec read and write functions in the MSCC PHY driver
    to remove the conditional locking.

Since v3:
  - Fixed a check when enabling offloading that was too restrictive.
  - Fixed the propagation of the changelink event to the underlying
    device drivers.

Since v2:
  - Allow selection the offloading from userspace, defaulting to the
    software implementation when adding a new MACsec interface. The
    offloading mode is now also reported through netlink.
  - Added support for letting MKA packets in and out when using MACsec
    (there are rules to let them bypass the MACsec h/w engine within the
    PHY).
  - Added support for PN rollover (following what's currently done in
    the software implementation: the flow is disabled).
  - Split patches to remove MAC offloading support for now, as there are
    no current provider for this (patches are still included).
  - Improved a few parts of the MACsec support within the MSCC PHY
    driver (e.g. default rules now block non-MACsec traffic, depending
    on the configuration).
  - Many cosmetic fixes & small improvements.

Since v1:
  - Reworked the MACsec offloading API, moving from a single helper
    called for all MACsec configuration operations, to a per-operation
    function that is provided by the underlying hardware drivers.
  - Those functions now contain a verb to describe the configuration
    action they're offloading.
  - Improved the error handling in the MACsec genl helpers to revert
    the configuration to its previous state when the offloading call
    failed.
  - Reworked the file inclusions.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 169af346 781449a4

drivers/net/macsec.c

+603 −184

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drivers/net/phy/Kconfig

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@@ -437,6 +437,9 @@ config MICROCHIP_T1_PHY 


config MICROSEMI_PHY

	tristate "Microsemi PHYs"

	depends on MACSEC || MACSEC=n

	select CRYPTO_AES

	select CRYPTO_ECB

	---help---

	  Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs

drivers/net/phy/mscc.c

+1132 −1

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drivers/net/phy/mscc_fc_buffer.h

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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */

/*

 * Microsemi Ocelot Switch driver

 *

 * Copyright (C) 2019 Microsemi Corporation

 */



#ifndef _MSCC_OCELOT_FC_BUFFER_H_

#define _MSCC_OCELOT_FC_BUFFER_H_



#define MSCC_FCBUF_ENA_CFG					0x00

#define MSCC_FCBUF_MODE_CFG					0x01

#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG			0x02

#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG				0x03

#define MSCC_FCBUF_TX_DATA_QUEUE_CFG				0x04

#define MSCC_FCBUF_RX_DATA_QUEUE_CFG				0x05

#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG			0x06

#define MSCC_FCBUF_FC_READ_THRESH_CFG				0x07

#define MSCC_FCBUF_TX_FRM_GAP_COMP				0x08



#define MSCC_FCBUF_ENA_CFG_TX_ENA				BIT(0)

#define MSCC_FCBUF_ENA_CFG_RX_ENA				BIT(4)



#define MSCC_FCBUF_MODE_CFG_DROP_BEHAVIOUR			BIT(4)

#define MSCC_FCBUF_MODE_CFG_PAUSE_REACT_ENA			BIT(8)

#define MSCC_FCBUF_MODE_CFG_RX_PPM_RATE_ADAPT_ENA		BIT(12)

#define MSCC_FCBUF_MODE_CFG_TX_PPM_RATE_ADAPT_ENA		BIT(16)

#define MSCC_FCBUF_MODE_CFG_TX_CTRL_QUEUE_ENA			BIT(20)

#define MSCC_FCBUF_MODE_CFG_PAUSE_GEN_ENA			BIT(24)

#define MSCC_FCBUF_MODE_CFG_INCLUDE_PAUSE_RCVD_IN_PAUSE_GEN	BIT(28)



#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH(x)	(x)

#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH_M	GENMASK(15, 0)

#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET(x)	((x) << 16)

#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET_M	GENMASK(19, 16)

#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_RX_THRESH(x)	((x) << 20)

#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_RX_THRESH_M	GENMASK(31, 20)



#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_START(x)			(x)

#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_START_M			GENMASK(15, 0)

#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_END(x)			((x) << 16)

#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_END_M			GENMASK(31, 16)



#define MSCC_FCBUF_TX_DATA_QUEUE_CFG_START(x)			(x)

#define MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M			GENMASK(15, 0)

#define MSCC_FCBUF_TX_DATA_QUEUE_CFG_END(x)			((x) << 16)

#define MSCC_FCBUF_TX_DATA_QUEUE_CFG_END_M			GENMASK(31, 16)



#define MSCC_FCBUF_RX_DATA_QUEUE_CFG_START(x)			(x)

#define MSCC_FCBUF_RX_DATA_QUEUE_CFG_START_M			GENMASK(15, 0)

#define MSCC_FCBUF_RX_DATA_QUEUE_CFG_END(x)			((x) << 16)

#define MSCC_FCBUF_RX_DATA_QUEUE_CFG_END_M			GENMASK(31, 16)



#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XOFF_THRESH(x)	(x)

#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XOFF_THRESH_M	GENMASK(15, 0)

#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XON_THRESH(x)	((x) << 16)

#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XON_THRESH_M	GENMASK(31, 16)



#define MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH(x)		(x)

#define MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH_M		GENMASK(15, 0)

#define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH(x)		((x) << 16)

#define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH_M		GENMASK(31, 16)



#endif

drivers/net/phy/mscc_mac.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */

/*

 * Microsemi Ocelot Switch driver

 *

 * Copyright (c) 2017 Microsemi Corporation

 */



#ifndef _MSCC_OCELOT_LINE_MAC_H_

#define _MSCC_OCELOT_LINE_MAC_H_



#define MSCC_MAC_CFG_ENA_CFG					0x00

#define MSCC_MAC_CFG_MODE_CFG					0x01

#define MSCC_MAC_CFG_MAXLEN_CFG					0x02

#define MSCC_MAC_CFG_NUM_TAGS_CFG				0x03

#define MSCC_MAC_CFG_TAGS_CFG					0x04

#define MSCC_MAC_CFG_ADV_CHK_CFG				0x07

#define MSCC_MAC_CFG_LFS_CFG					0x08

#define MSCC_MAC_CFG_LB_CFG					0x09

#define MSCC_MAC_CFG_PKTINF_CFG					0x0a

#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL			0x0b

#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_2			0x0c

#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL			0x0d

#define MSCC_MAC_PAUSE_CFG_STATE				0x0e

#define MSCC_MAC_PAUSE_CFG_MAC_ADDRESS_LSB			0x0f

#define MSCC_MAC_PAUSE_CFG_MAC_ADDRESS_MSB			0x10

#define MSCC_MAC_STATUS_RX_LANE_STICKY_0			0x11

#define MSCC_MAC_STATUS_RX_LANE_STICKY_1			0x12

#define MSCC_MAC_STATUS_TX_MONITOR_STICKY			0x13

#define MSCC_MAC_STATUS_TX_MONITOR_STICKY_MASK			0x14

#define MSCC_MAC_STATUS_STICKY					0x15

#define MSCC_MAC_STATUS_STICKY_MASK				0x16

#define MSCC_MAC_STATS_32BIT_RX_HIH_CKSM_ERR_CNT		0x17

#define MSCC_MAC_STATS_32BIT_RX_XGMII_PROT_ERR_CNT		0x18

#define MSCC_MAC_STATS_32BIT_RX_SYMBOL_ERR_CNT			0x19

#define MSCC_MAC_STATS_32BIT_RX_PAUSE_CNT			0x1a

#define MSCC_MAC_STATS_32BIT_RX_UNSUP_OPCODE_CNT		0x1b

#define MSCC_MAC_STATS_32BIT_RX_UC_CNT				0x1c

#define MSCC_MAC_STATS_32BIT_RX_MC_CNT				0x1d

#define MSCC_MAC_STATS_32BIT_RX_BC_CNT				0x1e

#define MSCC_MAC_STATS_32BIT_RX_CRC_ERR_CNT			0x1f

#define MSCC_MAC_STATS_32BIT_RX_UNDERSIZE_CNT			0x20

#define MSCC_MAC_STATS_32BIT_RX_FRAGMENTS_CNT			0x21

#define MSCC_MAC_STATS_32BIT_RX_IN_RANGE_LEN_ERR_CNT		0x22

#define MSCC_MAC_STATS_32BIT_RX_OUT_OF_RANGE_LEN_ERR_CNT	0x23

#define MSCC_MAC_STATS_32BIT_RX_OVERSIZE_CNT			0x24

#define MSCC_MAC_STATS_32BIT_RX_JABBERS_CNT			0x25

#define MSCC_MAC_STATS_32BIT_RX_SIZE64_CNT			0x26

#define MSCC_MAC_STATS_32BIT_RX_SIZE65TO127_CNT			0x27

#define MSCC_MAC_STATS_32BIT_RX_SIZE128TO255_CNT		0x28

#define MSCC_MAC_STATS_32BIT_RX_SIZE256TO511_CNT		0x29

#define MSCC_MAC_STATS_32BIT_RX_SIZE512TO1023_CNT		0x2a

#define MSCC_MAC_STATS_32BIT_RX_SIZE1024TO1518_CNT		0x2b

#define MSCC_MAC_STATS_32BIT_RX_SIZE1519TOMAX_CNT		0x2c

#define MSCC_MAC_STATS_32BIT_RX_IPG_SHRINK_CNT			0x2d

#define MSCC_MAC_STATS_32BIT_TX_PAUSE_CNT			0x2e

#define MSCC_MAC_STATS_32BIT_TX_UC_CNT				0x2f

#define MSCC_MAC_STATS_32BIT_TX_MC_CNT				0x30

#define MSCC_MAC_STATS_32BIT_TX_BC_CNT				0x31

#define MSCC_MAC_STATS_32BIT_TX_SIZE64_CNT			0x32

#define MSCC_MAC_STATS_32BIT_TX_SIZE65TO127_CNT			0x33

#define MSCC_MAC_STATS_32BIT_TX_SIZE128TO255_CNT		0x34

#define MSCC_MAC_STATS_32BIT_TX_SIZE256TO511_CNT		0x35

#define MSCC_MAC_STATS_32BIT_TX_SIZE512TO1023_CNT		0x36

#define MSCC_MAC_STATS_32BIT_TX_SIZE1024TO1518_CNT		0x37

#define MSCC_MAC_STATS_32BIT_TX_SIZE1519TOMAX_CNT		0x38

#define MSCC_MAC_STATS_40BIT_RX_BAD_BYTES_CNT			0x39

#define MSCC_MAC_STATS_40BIT_RX_BAD_BYTES_MSB_CNT		0x3a

#define MSCC_MAC_STATS_40BIT_RX_OK_BYTES_CNT			0x3b

#define MSCC_MAC_STATS_40BIT_RX_OK_BYTES_MSB_CNT		0x3c

#define MSCC_MAC_STATS_40BIT_RX_IN_BYTES_CNT			0x3d

#define MSCC_MAC_STATS_40BIT_RX_IN_BYTES_MSB_CNT		0x3e

#define MSCC_MAC_STATS_40BIT_TX_OK_BYTES_CNT			0x3f

#define MSCC_MAC_STATS_40BIT_TX_OK_BYTES_MSB_CNT		0x40

#define MSCC_MAC_STATS_40BIT_TX_OUT_BYTES_CNT			0x41

#define MSCC_MAC_STATS_40BIT_TX_OUT_BYTES_MSB_CNT		0x42



#define MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA				BIT(0)

#define MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA				BIT(4)

#define MSCC_MAC_CFG_ENA_CFG_RX_SW_RST				BIT(8)

#define MSCC_MAC_CFG_ENA_CFG_TX_SW_RST				BIT(12)

#define MSCC_MAC_CFG_ENA_CFG_RX_ENA				BIT(16)

#define MSCC_MAC_CFG_ENA_CFG_TX_ENA				BIT(20)



#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE_INTERVAL(x)	((x) << 20)

#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE_INTERVAL_M	GENMASK(29, 20)

#define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE			BIT(16)

#define MSCC_MAC_CFG_MODE_CFG_TUNNEL_PAUSE_FRAMES		BIT(14)

#define MSCC_MAC_CFG_MODE_CFG_MAC_PREAMBLE_CFG(x)		((x) << 10)

#define MSCC_MAC_CFG_MODE_CFG_MAC_PREAMBLE_CFG_M		GENMASK(12, 10)

#define MSCC_MAC_CFG_MODE_CFG_MAC_IPG_CFG			BIT(6)

#define MSCC_MAC_CFG_MODE_CFG_XGMII_GEN_MODE_ENA		BIT(4)

#define MSCC_MAC_CFG_MODE_CFG_HIH_CRC_CHECK			BIT(2)

#define MSCC_MAC_CFG_MODE_CFG_UNDERSIZED_FRAME_DROP_DIS		BIT(1)

#define MSCC_MAC_CFG_MODE_CFG_DISABLE_DIC			BIT(0)



#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_TAG_CHK			BIT(16)

#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN(x)			(x)

#define MSCC_MAC_CFG_MAXLEN_CFG_MAX_LEN_M			GENMASK(15, 0)



#define MSCC_MAC_CFG_TAGS_CFG_RSZ				0x4

#define MSCC_MAC_CFG_TAGS_CFG_TAG_ID(x)				((x) << 16)

#define MSCC_MAC_CFG_TAGS_CFG_TAG_ID_M				GENMASK(31, 16)

#define MSCC_MAC_CFG_TAGS_CFG_TAG_ENA				BIT(4)



#define MSCC_MAC_CFG_ADV_CHK_CFG_EXT_EOP_CHK_ENA		BIT(24)

#define MSCC_MAC_CFG_ADV_CHK_CFG_EXT_SOP_CHK_ENA		BIT(20)

#define MSCC_MAC_CFG_ADV_CHK_CFG_SFD_CHK_ENA			BIT(16)

#define MSCC_MAC_CFG_ADV_CHK_CFG_PRM_SHK_CHK_DIS		BIT(12)

#define MSCC_MAC_CFG_ADV_CHK_CFG_PRM_CHK_ENA			BIT(8)

#define MSCC_MAC_CFG_ADV_CHK_CFG_OOR_ERR_ENA			BIT(4)

#define MSCC_MAC_CFG_ADV_CHK_CFG_INR_ERR_ENA			BIT(0)



#define MSCC_MAC_CFG_LFS_CFG_LFS_INH_TX				BIT(8)

#define MSCC_MAC_CFG_LFS_CFG_LFS_DIS_TX				BIT(4)

#define MSCC_MAC_CFG_LFS_CFG_LFS_UNIDIR_ENA			BIT(3)

#define MSCC_MAC_CFG_LFS_CFG_USE_LEADING_EDGE_DETECT		BIT(2)

#define MSCC_MAC_CFG_LFS_CFG_SPURIOUS_Q_DIS			BIT(1)

#define MSCC_MAC_CFG_LFS_CFG_LFS_MODE_ENA			BIT(0)



#define MSCC_MAC_CFG_LB_CFG_XGMII_HOST_LB_ENA			BIT(4)

#define MSCC_MAC_CFG_LB_CFG_XGMII_PHY_LB_ENA			BIT(0)



#define MSCC_MAC_CFG_PKTINF_CFG_STRIP_FCS_ENA			BIT(0)

#define MSCC_MAC_CFG_PKTINF_CFG_INSERT_FCS_ENA			BIT(4)

#define MSCC_MAC_CFG_PKTINF_CFG_STRIP_PREAMBLE_ENA		BIT(8)

#define MSCC_MAC_CFG_PKTINF_CFG_INSERT_PREAMBLE_ENA		BIT(12)

#define MSCC_MAC_CFG_PKTINF_CFG_LPI_RELAY_ENA			BIT(16)

#define MSCC_MAC_CFG_PKTINF_CFG_LF_RELAY_ENA			BIT(20)

#define MSCC_MAC_CFG_PKTINF_CFG_RF_RELAY_ENA			BIT(24)

#define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_TX_PADDING		BIT(25)

#define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_RX_PADDING		BIT(26)

#define MSCC_MAC_CFG_PKTINF_CFG_ENABLE_4BYTE_PREAMBLE		BIT(27)

#define MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS(x)	((x) << 28)

#define MSCC_MAC_CFG_PKTINF_CFG_MACSEC_BYPASS_NUM_PTP_STALL_CLKS_M	GENMASK(30, 28)



#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE(x)		((x) << 16)

#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_VALUE_M		GENMASK(31, 16)

#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_WAIT_FOR_LPI_LOW	BIT(12)

#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_USE_PAUSE_STALL_ENA	BIT(8)

#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_REPL_MODE	BIT(4)

#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_FRC_FRAME	BIT(2)

#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE(x)		(x)

#define MSCC_MAC_PAUSE_CFG_TX_FRAME_CTRL_PAUSE_MODE_M		GENMASK(1, 0)



#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_EARLY_PAUSE_DETECT_ENA	BIT(16)

#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PRE_CRC_MODE		BIT(20)

#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_TIMER_ENA	BIT(12)

#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_REACT_ENA	BIT(8)

#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_FRAME_DROP_ENA	BIT(4)

#define MSCC_MAC_PAUSE_CFG_RX_FRAME_CTRL_PAUSE_MODE		BIT(0)



#define MSCC_MAC_PAUSE_CFG_STATE_PAUSE_STATE			BIT(0)

#define MSCC_MAC_PAUSE_CFG_STATE_MAC_TX_PAUSE_GEN		BIT(4)



#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL			0x2

#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE(x)	(x)

#define MSCC_PROC_0_IP_1588_TOP_CFG_STAT_MODE_CTL_PROTOCOL_MODE_M	GENMASK(2, 0)



#endif /* _MSCC_OCELOT_LINE_MAC_H_ */

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