Commit ec1e1264 authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915/tgl: Implement Wa_1409804808 



This workaround the CS not done issue on PIPE_CONTROL.

v2:
- replaced BIT() by REG_BIT() in all GEN7_ROW_CHICKEN2() bits
- shortened the name of the new bit

BSpec: 52890
BSpec: 46218
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200227220101.321671-1-jose.souza@intel.com
parent ccc495fd

drivers/gpu/drm/i915/gt/intel_workarounds.c

+6 −0
Original line number Diff line number Diff line
@@ -1362,6 +1362,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
			     GEN12_DISABLE_EARLY_READ);

	}



	if (IS_TIGERLAKE(i915)) {

		/* Wa_1409804808:tgl */

		wa_masked_en(wal, GEN7_ROW_CHICKEN2,

			     GEN12_PUSH_CONST_DEREF_HOLD_DIS);

	}



	if (IS_GEN(i915, 11)) {

		/* This is not an Wa. Enable for better image quality */

		wa_masked_en(wal,

drivers/gpu/drm/i915/i915_reg.h

+3 −2
Original line number Diff line number Diff line
@@ -9141,7 +9141,8 @@ enum { 
#define   DISABLE_EARLY_EOT			(1 << 1)



#define GEN7_ROW_CHICKEN2			_MMIO(0xe4f4)

#define GEN12_DISABLE_EARLY_READ	BIT(14)

#define   GEN12_DISABLE_EARLY_READ		REG_BIT(14)

#define   GEN12_PUSH_CONST_DEREF_HOLD_DIS	REG_BIT(8)



#define GEN7_ROW_CHICKEN2_GT2		_MMIO(0xf4f4)

#define   DOP_CLOCK_GATING_DISABLE	(1 << 0)

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