Commit ec16ffe3 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' into clk-next 

 - Support CGU in Ingenix X1000
 - Support Bitmain BM1880 clks

* clk-ingenic:
  clk: ingenic: Allow drivers to be built with COMPILE_TEST
  clk: Ingenic: Add CGU driver for X1000.
  dt-bindings: clock: Add X1000 bindings.

* clk-init-leak:
  clk: mark clk_disable_unused() as __init
  clk: Fix memory leak in clk_unregister()

* clk-ux500:
  MAINTAINERS: Update section for Ux500 clock drivers

* clk-bitmain:
  MAINTAINERS: Add entry for BM1880 SoC clock driver
  clk: Add common clock driver for BM1880 SoC
  dt-bindings: clock: Add devicetree binding for BM1880 SoC
  clk: Add clk_hw_unregister_composite helper function definition
  clk: Zero init clk_init_data in helpers
parents dabedfed cd94eade 564f86d3 8f39f22f 1e4fb2c0

Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/bindings/clock/bitmain,bm1880-clk.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Bitmain BM1880 Clock Controller



maintainers:

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>



description: |

  The Bitmain BM1880 clock controller generates and supplies clock to

  various peripherals within the SoC.



  This binding uses common clock bindings

  [1] Documentation/devicetree/bindings/clock/clock-bindings.txt



properties:

  compatible:

    const: bitmain,bm1880-clk



  reg:

    items:

      - description: pll registers

      - description: system registers



  reg-names:

    items:

      - const: pll

      - const: sys



  clocks:

    maxItems: 1



  clock-names:

    const: osc



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg

  - reg-names

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false



examples:

  # Clock controller node:

  - |

    clk: clock-controller@e8 {

        compatible = "bitmain,bm1880-clk";

        reg = <0xe8 0x0c>, <0x800 0xb0>;

        reg-names = "pll", "sys";

        clocks = <&osc>;

        clock-names = "osc";

        #clock-cells = <1>;

    };



  # Example UART controller node that consumes clock generated by the clock controller:

  - |

    uart0: serial@58018000 {

         compatible = "snps,dw-apb-uart";

         reg = <0x0 0x58018000 0x0 0x2000>;

         clocks = <&clk 45>, <&clk 46>;

         clock-names = "baudclk", "apb_pclk";

         interrupts = <0 9 4>;

         reg-shift = <2>;

         reg-io-width = <4>;

    };



...

Documentation/devicetree/bindings/clock/ingenic,cgu.txt

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@@ -11,6 +11,7 @@ Required properties: 
  * ingenic,jz4725b-cgu

  * ingenic,jz4770-cgu

  * ingenic,jz4780-cgu

  * ingenic,x1000-cgu

- reg : The address & length of the CGU registers.

- clocks : List of phandle & clock specifiers for clocks external to the CGU.

  Two such external clocks should be specified - first the external crystal

MAINTAINERS

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@@ -1529,8 +1529,10 @@ M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 
L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

F:	arch/arm64/boot/dts/bitmain/

F:	drivers/clk/clk-bm1880.c

F:	drivers/pinctrl/pinctrl-bm1880.c

F:	Documentation/devicetree/bindings/arm/bitmain.yaml

F:	Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml

F:	Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.txt















ARM/CALXEDA HIGHBANK ARCHITECTURE










@@ -2490,10 +2492,10 @@ F:	drivers/reset/reset-uniphier.c













F:	drivers/tty/serial/8250/8250_uniphier.c















N:	uniphier



























ARM/Ux500 CLOCK FRAMEWORK SUPPORT













Ux500 CLOCK DRIVERS















M:	Ulf Hansson <ulf.hansson@linaro.org>













L:	linux-clk@vger.kernel.org















L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)













T:	git git://git.linaro.org/people/ulfh/clk.git















S:	Maintained















F:	drivers/clk/ux500/















































drivers/clk/Kconfig



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−0






























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@@ -136,6 +136,13 @@ config COMMON_CLK_SI570













	  This driver supports Silicon Labs 570/571/598/599 programmable















	  clock generators.





























config COMMON_CLK_BM1880













	bool "Clock driver for Bitmain BM1880 SoC"













	depends on ARCH_BITMAIN || COMPILE_TEST













	default ARCH_BITMAIN













	help













	  This driver supports the clocks on Bitmain BM1880 SoC.





























config COMMON_CLK_CDCE706















	tristate "Clock driver for TI CDCE706 clock synthesizer"















	depends on I2C

































drivers/clk/Makefile



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@@ -22,6 +22,7 @@ obj-$(CONFIG_MACH_ASM9260)		+= clk-asm9260.o













obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)	+= clk-axi-clkgen.o















obj-$(CONFIG_ARCH_AXXIA)		+= clk-axm5516.o















obj-$(CONFIG_COMMON_CLK_BD718XX)	+= clk-bd718x7.o













obj-$(CONFIG_COMMON_CLK_BM1880)		+= clk-bm1880.o















obj-$(CONFIG_COMMON_CLK_CDCE706)	+= clk-cdce706.o















obj-$(CONFIG_COMMON_CLK_CDCE925)	+= clk-cdce925.o















obj-$(CONFIG_ARCH_CLPS711X)		+= clk-clps711x.o









































































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