Commit ebf5a248 authored by Matthew Wilcox's avatar Matthew Wilcox Committed by Greg Kroah-Hartman
Browse files

PCI: Use pci_generic_prep_mwi on sparc64 



The setting of the CACHE_LINE_SIZE register in sparc64's pci
initialisation code isn't quite adequate as the device may have
incompatible requirements.  The generic code tests for this, so switch
sparc64 over to using it.

Since sparc64 has different L1 cache line size and PCI cache line size,
it would need to override the generic code like i386 and ia64 do.  We
know what the cache line size is at compile time though, so introduce a
new optional constant PCI_CACHE_LINE_BYTES.

Signed-off-by: default avatarMatthew Wilcox <matthew@wil.cx>
Signed-off-by: default avatarDavid Miller <davem@davemloft.net>
Acked-by: default avatarJeff Garzik <jeff@garzik.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 3efe2d84

arch/sparc64/kernel/pci.c

+0 −9
Original line number Diff line number Diff line
@@ -646,13 +646,4 @@ int pci_domain_nr(struct pci_bus *pbus) 
}

EXPORT_SYMBOL(pci_domain_nr);



int pcibios_prep_mwi(struct pci_dev *dev)

{

	/* We set correct PCI_CACHE_LINE_SIZE register values for every

	 * device probed on this platform.  So there is nothing to check

	 * and this always succeeds.

	 */

	return 0;

}



#endif /* !(CONFIG_PCI) */

drivers/pci/pci.c

+7 −1
Original line number Diff line number Diff line
@@ -876,8 +876,14 @@ pci_set_master(struct pci_dev *dev) 
}



#ifndef HAVE_ARCH_PCI_MWI



#ifndef PCI_CACHE_LINE_BYTES

#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES

#endif



/* This can be overridden by arch code. */

u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;

/* Don't forget this is measured in 32-bit words, not bytes */

u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;



/**

 * pci_generic_prep_mwi - helper function for pci_set_mwi

include/asm-sparc64/pci.h

+2 −4
Original line number Diff line number Diff line
@@ -18,6 +18,8 @@ 


#define PCI_IRQ_NONE		0xffffffff



#define PCI_CACHE_LINE_BYTES	64



static inline void pcibios_set_master(struct pci_dev *dev)

{

	/* No special bus mastering setup handling */
@@ -291,10 +293,6 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 
			       enum pci_mmap_state mmap_state,

			       int write_combine);



/* Platform specific MWI support. */

#define HAVE_ARCH_PCI_MWI

extern int pcibios_prep_mwi(struct pci_dev *dev);



extern void

pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,

			struct resource *res);

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