Unverified Commit ebe04bfe authored by Tudor Ambarus's avatar Tudor Ambarus
Browse files

mtd: spi-nor: Stop compare with negative in Reg Ops methods 



spi_mem_exec_op()
nor->controller_ops->write_reg()
nor->controller_ops->read_reg()
spi_nor_wait_till_ready()
Return 0 on success, -errno otherwise.

Stop compare with negative and compare with zero in all the register
operations methods.

Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: default avatarBoris Brezillon <boris.brezillon@collabora.com>
parent 502c4b0a

drivers/mtd/spi-nor/spi-nor.c

+13 −10
Original line number Diff line number Diff line
@@ -447,7 +447,7 @@ static int spi_nor_read_sr(struct spi_nor *nor) 
						    nor->bouncebuf, 1);

	}



	if (ret < 0) {

	if (ret) {

		pr_err("error %d reading SR\n", (int) ret);

		return ret;

	}
@@ -477,7 +477,7 @@ static int spi_nor_read_fsr(struct spi_nor *nor) 
						    nor->bouncebuf, 1);

	}



	if (ret < 0) {

	if (ret) {

		pr_err("error %d reading FSR\n", ret);

		return ret;

	}
@@ -507,7 +507,7 @@ static int spi_nor_read_cr(struct spi_nor *nor) 
						    nor->bouncebuf, 1);

	}



	if (ret < 0) {

	if (ret) {

		dev_err(nor->dev, "error %d reading CR\n", ret);

		return ret;

	}
@@ -643,7 +643,7 @@ static int s3an_sr_ready(struct spi_nor *nor) 
	int ret;



	ret = spi_nor_xread_sr(nor, nor->bouncebuf);

	if (ret < 0) {

	if (ret) {

		dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);

		return ret;

	}
@@ -800,7 +800,7 @@ static int spi_nor_write_sr_cr(struct spi_nor *nor, u8 *sr_cr) 
						     sr_cr, 2);

	}



	if (ret < 0) {

	if (ret) {

		dev_err(nor->dev,

			"error while writing configuration register\n");

		return -EINVAL;
@@ -1930,20 +1930,23 @@ static int sr2_bit7_quad_enable(struct spi_nor *nor) 
	spi_nor_write_enable(nor);



	ret = spi_nor_write_sr2(nor, sr2);

	if (ret < 0) {

	if (ret) {

		dev_err(nor->dev, "error while writing status register 2\n");

		return -EINVAL;

	}



	ret = spi_nor_wait_till_ready(nor);

	if (ret < 0) {

	if (ret) {

		dev_err(nor->dev, "timeout while writing status register 2\n");

		return ret;

	}



	/* Read back and check it. */

	ret = spi_nor_read_sr2(nor, sr2);

	if (!(ret > 0 && (*sr2 & SR2_QUAD_EN_BIT7))) {

	if (ret)

		return ret;



	if (!(*sr2 & SR2_QUAD_EN_BIT7)) {

		dev_err(nor->dev, "SR2 Quad bit not set\n");

		return -EINVAL;

	}
@@ -2534,7 +2537,7 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) 
		tmp = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,

						    SPI_NOR_MAX_ID_LEN);

	}

	if (tmp < 0) {

	if (tmp) {

		dev_err(nor->dev, "error %d reading JEDEC ID\n", tmp);

		return ERR_PTR(tmp);

	}
@@ -2751,7 +2754,7 @@ static int s3an_nor_setup(struct spi_nor *nor, 
	int ret;



	ret = spi_nor_xread_sr(nor, nor->bouncebuf);

	if (ret < 0) {

	if (ret) {

		dev_err(nor->dev, "error %d reading XRDSR\n", (int) ret);

		return ret;

	}

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