Commit ebd4050c authored Jul 09, 2020 by Eddie James Committed by Ulf Hansson Jul 13, 2020

mmc: sdhci-of-aspeed: Fix clock divider calculation



When calculating the clock divider, start dividing at 2 instead of 1.
The divider is divided by two at the end of the calculation, so starting
at 1 may result in a divider of 0, which shouldn't happen.

Signed-off-by: Eddie James <eajames@linux.ibm.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20200709195706.12741-3-eajames@linux.ibm.com


Cc: stable@vger.kernel.org # v5.4+
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

parent 11ba4688

drivers/mmc/host/sdhci-of-aspeed.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -68,7 +68,7 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
		if (WARN_ON(clock > host->max_clk))
		clock = host->max_clk;

		for (div = 1; div < 256; div *= 2) {
		for (div = 2; div < 256; div *= 2) {
		if ((parent / div) <= clock)
		break;
		}

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