Commit eb81b249 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/enumeration' 

  - Add PCIe 32 GT/s speed decoding for sysfs "max_link_speed" and dmesg
    notes about available bandwidth (Yicong Yang)

  - Simplify and unify PCI bus/link speed reporting (Yicong Yang)

* pci/enumeration:
  PCI: Add PCIE_LNKCAP2_SLS2SPEED() macro
  PCI: Use pci_speed_string() for all PCI/PCI-X/PCIe strings
  PCI: Add pci_speed_string()
  PCI: Add 32 GT/s decoding in some macros
parents 4ea40c38 757bfaa2

drivers/pci/controller/pcie-brcmstb.c

+2 −2
Original line number Diff line number Diff line
@@ -824,8 +824,8 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) 
	cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta);

	nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);

	dev_info(dev, "link up, %s x%u %s\n",

		 PCIE_SPEED2STR(cls + PCI_SPEED_133MHz_PCIX_533),

		 nlw, ssc_good ? "(SSC)" : "(!SSC)");

		 pci_speed_string(pcie_link_speed[cls]), nlw,

		 ssc_good ? "(SSC)" : "(!SSC)");



	/* PCIe->SCB endian mode for BAR */

	tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);

drivers/pci/pci-sysfs.c

+5 −22
Original line number Diff line number Diff line
@@ -156,7 +156,8 @@ static ssize_t max_link_speed_show(struct device *dev, 
{

	struct pci_dev *pdev = to_pci_dev(dev);



	return sprintf(buf, "%s\n", PCIE_SPEED2STR(pcie_get_speed_cap(pdev)));

	return sprintf(buf, "%s\n",

		       pci_speed_string(pcie_get_speed_cap(pdev)));

}

static DEVICE_ATTR_RO(max_link_speed);
@@ -175,33 +176,15 @@ static ssize_t current_link_speed_show(struct device *dev, 
	struct pci_dev *pci_dev = to_pci_dev(dev);

	u16 linkstat;

	int err;

	const char *speed;

	enum pci_bus_speed speed;



	err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat);

	if (err)

		return -EINVAL;



	switch (linkstat & PCI_EXP_LNKSTA_CLS) {

	case PCI_EXP_LNKSTA_CLS_32_0GB:

		speed = "32 GT/s";

		break;

	case PCI_EXP_LNKSTA_CLS_16_0GB:

		speed = "16 GT/s";

		break;

	case PCI_EXP_LNKSTA_CLS_8_0GB:

		speed = "8 GT/s";

		break;

	case PCI_EXP_LNKSTA_CLS_5_0GB:

		speed = "5 GT/s";

		break;

	case PCI_EXP_LNKSTA_CLS_2_5GB:

		speed = "2.5 GT/s";

		break;

	default:

		speed = "Unknown speed";

	}



	return sprintf(buf, "%s\n", speed);

	speed = pcie_link_speed[linkstat & PCI_EXP_LNKSTA_CLS];



	return sprintf(buf, "%s\n", pci_speed_string(speed));

}

static DEVICE_ATTR_RO(current_link_speed);

drivers/pci/pci.c

+7 −16
Original line number Diff line number Diff line
@@ -5784,19 +5784,10 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) 
	 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.

	 */

	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);

	if (lnkcap2) { /* PCIe r3.0-compliant */

		if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB)

			return PCIE_SPEED_32_0GT;

		else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)

			return PCIE_SPEED_16_0GT;

		else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)

			return PCIE_SPEED_8_0GT;

		else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)

			return PCIE_SPEED_5_0GT;

		else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)

			return PCIE_SPEED_2_5GT;

		return PCI_SPEED_UNKNOWN;

	}



	/* PCIe r3.0-compliant */

	if (lnkcap2)

		return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);



	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);

	if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
@@ -5872,14 +5863,14 @@ void __pcie_print_link_status(struct pci_dev *dev, bool verbose) 
	if (bw_avail >= bw_cap && verbose)

		pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",

			 bw_cap / 1000, bw_cap % 1000,

			 PCIE_SPEED2STR(speed_cap), width_cap);

			 pci_speed_string(speed_cap), width_cap);

	else if (bw_avail < bw_cap)

		pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",

			 bw_avail / 1000, bw_avail % 1000,

			 PCIE_SPEED2STR(speed), width,

			 pci_speed_string(speed), width,

			 limiting_dev ? pci_name(limiting_dev) : "<unknown>",

			 bw_cap / 1000, bw_cap % 1000,

			 PCIE_SPEED2STR(speed_cap), width_cap);

			 pci_speed_string(speed_cap), width_cap);

}



/**

drivers/pci/pci.h

+11 −8
Original line number Diff line number Diff line
@@ -292,22 +292,25 @@ void pci_disable_bridge_window(struct pci_dev *dev); 
struct pci_bus *pci_bus_get(struct pci_bus *bus);

void pci_bus_put(struct pci_bus *bus);



/* PCIe link information */

#define PCIE_SPEED2STR(speed) \

	((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \

	 (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \

	 (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \

	 (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \

	 "Unknown speed")

/* PCIe link information from Link Capabilities 2 */

#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \

	((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \

	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \

	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \

	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \

	 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \

	 PCI_SPEED_UNKNOWN)



/* PCIe speed to Mb/s reduced by encoding overhead */

#define PCIE_SPEED2MBS_ENC(speed) \

	((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \

	((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \

	 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \

	 (speed) == PCIE_SPEED_8_0GT  ?  8000*128/130 : \

	 (speed) == PCIE_SPEED_5_0GT  ?  5000*8/10 : \

	 (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \

	 0)



const char *pci_speed_string(enum pci_bus_speed speed);

enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);

enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);

u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,

drivers/pci/probe.c

+40 −0
Original line number Diff line number Diff line
@@ -641,6 +641,7 @@ void pci_free_host_bridge(struct pci_host_bridge *bridge) 
}

EXPORT_SYMBOL(pci_free_host_bridge);



/* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */

static const unsigned char pcix_bus_speed[] = {

	PCI_SPEED_UNKNOWN,		/* 0 */

	PCI_SPEED_66MHz_PCIX,		/* 1 */
@@ -660,6 +661,7 @@ static const unsigned char pcix_bus_speed[] = { 
	PCI_SPEED_133MHz_PCIX_533	/* F */

};



/* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */

const unsigned char pcie_link_speed[] = {

	PCI_SPEED_UNKNOWN,		/* 0 */

	PCIE_SPEED_2_5GT,		/* 1 */
@@ -678,6 +680,44 @@ const unsigned char pcie_link_speed[] = { 
	PCI_SPEED_UNKNOWN,		/* E */

	PCI_SPEED_UNKNOWN		/* F */

};

EXPORT_SYMBOL_GPL(pcie_link_speed);



const char *pci_speed_string(enum pci_bus_speed speed)

{

	/* Indexed by the pci_bus_speed enum */

	static const char *speed_strings[] = {

	    "33 MHz PCI",		/* 0x00 */

	    "66 MHz PCI",		/* 0x01 */

	    "66 MHz PCI-X",		/* 0x02 */

	    "100 MHz PCI-X",		/* 0x03 */

	    "133 MHz PCI-X",		/* 0x04 */

	    NULL,			/* 0x05 */

	    NULL,			/* 0x06 */

	    NULL,			/* 0x07 */

	    NULL,			/* 0x08 */

	    "66 MHz PCI-X 266",		/* 0x09 */

	    "100 MHz PCI-X 266",	/* 0x0a */

	    "133 MHz PCI-X 266",	/* 0x0b */

	    "Unknown AGP",		/* 0x0c */

	    "1x AGP",			/* 0x0d */

	    "2x AGP",			/* 0x0e */

	    "4x AGP",			/* 0x0f */

	    "8x AGP",			/* 0x10 */

	    "66 MHz PCI-X 533",		/* 0x11 */

	    "100 MHz PCI-X 533",	/* 0x12 */

	    "133 MHz PCI-X 533",	/* 0x13 */

	    "2.5 GT/s PCIe",		/* 0x14 */

	    "5.0 GT/s PCIe",		/* 0x15 */

	    "8.0 GT/s PCIe",		/* 0x16 */

	    "16.0 GT/s PCIe",		/* 0x17 */

	    "32.0 GT/s PCIe",		/* 0x18 */

	};



	if (speed < ARRAY_SIZE(speed_strings))

		return speed_strings[speed];

	return "Unknown";

}

EXPORT_SYMBOL_GPL(pci_speed_string);



void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)

{

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