Commit eb7c825b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull RISC-V fixes from Paul Walmsley:
 "This contains fixes, defconfig, and DT data changes for the v5.2-rc
  series.

  The fixes are relatively straightforward:

   - Addition of a TLB fence in the vmalloc_fault path, so the CPU
     doesn't enter an infinite page fault loop

   - Readdition of the pm_power_off export, so device drivers that
     reassign it can now be built as modules

   - A udelay() fix for RV32, fixing a miscomputation of the delay time

   - Removal of deprecated smp_mb__*() barriers

  This also adds initial DT data infrastructure for arch/riscv, along
  with initial data for the SiFive FU540-C000 SoC and the corresponding
  HiFive Unleashed board.

  We also update the RV64 defconfig to include some core drivers for the
  FU540 in the build"

* tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: remove unused barrier defines
  riscv: mm: synchronize MMU after pte change
  riscv: dts: add initial board data for the SiFive HiFive Unleashed
  riscv: dts: add initial support for the SiFive FU540-C000 SoC
  dt-bindings: riscv: convert cpu binding to json-schema
  dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540
  arch: riscv: add support for building DTB files from DT source data
  riscv: Fix udelay in RV32.
  riscv: export pm_power_off again
  RISC-V: defconfig: enable clocks, serial console
parents 9e0babf2 259931fd

Documentation/devicetree/bindings/riscv/cpus.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR MIT)

%YAML 1.2

---

$id: http://devicetree.org/schemas/riscv/cpus.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: RISC-V bindings for 'cpus' DT nodes



maintainers:

  - Paul Walmsley <paul.walmsley@sifive.com>

  - Palmer Dabbelt <palmer@sifive.com>



allOf:

  - $ref: /schemas/cpus.yaml#



properties:

  $nodename:

    const: cpus

    description: Container of cpu nodes



  '#address-cells':

    const: 1

    description: |

      A single unsigned 32-bit integer uniquely identifies each RISC-V

      hart in a system.  (See the "reg" node under the "cpu" node,

      below).



  '#size-cells':

    const: 0



patternProperties:

  '^cpu@[0-9a-f]+$':

    properties:

      compatible:

        type: array

        items:

          - enum:

              - sifive,rocket0

              - sifive,e5

              - sifive,e51

              - sifive,u54-mc

              - sifive,u54

              - sifive,u5

          - const: riscv

        description:

          Identifies that the hart uses the RISC-V instruction set

          and identifies the type of the hart.



      mmu-type:

        allOf:

          - $ref: "/schemas/types.yaml#/definitions/string"

          - enum:

              - riscv,sv32

              - riscv,sv39

              - riscv,sv48

        description:

          Identifies the MMU address translation mode used on this

          hart.  These values originate from the RISC-V Privileged

          Specification document, available from

          https://riscv.org/specifications/



      riscv,isa:

        allOf:

          - $ref: "/schemas/types.yaml#/definitions/string"

          - enum:

              - rv64imac

              - rv64imafdc

        description:

          Identifies the specific RISC-V instruction set architecture

          supported by the hart.  These are documented in the RISC-V

          User-Level ISA document, available from

          https://riscv.org/specifications/



      timebase-frequency:

        type: integer

        minimum: 1

        description:

          Specifies the clock frequency of the system timer in Hz.

          This value is common to all harts on a single system image.



      interrupt-controller:

        type: object

        description: Describes the CPU's local interrupt controller



        properties:

          '#interrupt-cells':

            const: 1



          compatible:

            const: riscv,cpu-intc



          interrupt-controller: true



        required:

          - '#interrupt-cells'

          - compatible

          - interrupt-controller



    required:

      - riscv,isa

      - timebase-frequency

      - interrupt-controller



examples:

  - |

    // Example 1: SiFive Freedom U540G Development Kit

    cpus {

        #address-cells = <1>;

        #size-cells = <0>;

        timebase-frequency = <1000000>;

        cpu@0 {

                clock-frequency = <0>;

                compatible = "sifive,rocket0", "riscv";

                device_type = "cpu";

                i-cache-block-size = <64>;

                i-cache-sets = <128>;

                i-cache-size = <16384>;

                reg = <0>;

                riscv,isa = "rv64imac";

                cpu_intc0: interrupt-controller {

                        #interrupt-cells = <1>;

                        compatible = "riscv,cpu-intc";

                        interrupt-controller;

                };

        };

        cpu@1 {

                clock-frequency = <0>;

                compatible = "sifive,rocket0", "riscv";

                d-cache-block-size = <64>;

                d-cache-sets = <64>;

                d-cache-size = <32768>;

                d-tlb-sets = <1>;

                d-tlb-size = <32>;

                device_type = "cpu";

                i-cache-block-size = <64>;

                i-cache-sets = <64>;

                i-cache-size = <32768>;

                i-tlb-sets = <1>;

                i-tlb-size = <32>;

                mmu-type = "riscv,sv39";

                reg = <1>;

                riscv,isa = "rv64imafdc";

                tlb-split;

                cpu_intc1: interrupt-controller {

                        #interrupt-cells = <1>;

                        compatible = "riscv,cpu-intc";

                        interrupt-controller;

                };

        };

    };



  - |

    // Example 2: Spike ISA Simulator with 1 Hart

    cpus {

            cpu@0 {

                    device_type = "cpu";

                    reg = <0>;

                    compatible = "riscv";

                    riscv,isa = "rv64imafdc";

                    mmu-type = "riscv,sv48";

                    interrupt-controller {

                            #interrupt-cells = <1>;

                            interrupt-controller;

                            compatible = "riscv,cpu-intc";

                    };

            };

    };

...

Documentation/devicetree/bindings/riscv/sifive.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR MIT)

%YAML 1.2

---

$id: http://devicetree.org/schemas/riscv/sifive.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: SiFive SoC-based boards



maintainers:

  - Paul Walmsley <paul.walmsley@sifive.com>

  - Palmer Dabbelt <palmer@sifive.com>



description:

  SiFive SoC-based boards



properties:

  $nodename:

    const: '/'

  compatible:

    items:

      - enum:

          - sifive,freedom-unleashed-a00

      - const: sifive,fu540-c000

      - const: sifive,fu540

...

MAINTAINERS

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@@ -14335,6 +14335,15 @@ S: Supported 
K:	sifive

N:	sifive



SIFIVE FU540 SYSTEM-ON-CHIP

M:	Paul Walmsley <paul.walmsley@sifive.com>

M:	Palmer Dabbelt <palmer@sifive.com>

L:	linux-riscv@lists.infradead.org

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/pjw/sifive.git

S:	Supported

K:	fu540

N:	fu540



SILEAD TOUCHSCREEN DRIVER

M:	Hans de Goede <hdegoede@redhat.com>

L:	linux-input@vger.kernel.org

arch/riscv/boot/dts/Makefile

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# SPDX-License-Identifier: GPL-2.0

subdir-y += sifive

arch/riscv/boot/dts/sifive/Makefile

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# SPDX-License-Identifier: GPL-2.0

dtb-y += hifive-unleashed-a00.dtb

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