arm64: flush TLS registers during exec (eb35bdd7) · Commits · 戴 / test

Nathan reports that we leak TLS information from the parent context during an exec, as we don't clear the TLS registers when flushing the thread state. This patch updates the flushing code so that we: (1) Unconditionally zero the tpidr_el0 register (since this is fully context switched for native tasks and zeroed for compat tasks) (2) Zero the tp_value state in thread_info before clearing the tpidrr0_el0 register for compat tasks (since this is only writable by the set_tls compat syscall and therefore not fully switched). A missing compiler barrier is also added to the compat set_tls syscall. Cc: <stable@vger.kernel.org> Acked-by:

Nathan Lynch <Nathan_Lynch@mentor.com> Reported-by:

Nathan Lynch <Nathan_Lynch@mentor.com> Signed-off-by:

Will Deacon <will.deacon@arm.com>

arch/arm64/kernel/process.c

+18 −0

Original line number	Diff line number	Diff line
		@@ -230,9 +230,27 @@ void exit_thread(void)
		{
		}

		static void tls_thread_flush(void)
		{
		asm ("msr tpidr_el0, xzr");

		if (is_compat_task()) {
		current->thread.tp_value = 0;

		/*
		* We need to ensure ordering between the shadow state and the
		* hardware state, so that we don't corrupt the hardware state
		* with a stale shadow state during context switch.
		*/
		barrier();
		asm ("msr tpidrro_el0, xzr");
		}
		}

		void flush_thread(void)
		{
		fpsimd_flush_thread();
		tls_thread_flush();
		flush_ptrace_hw_breakpoint(current);
		}

arch/arm64/kernel/sys_compat.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -79,6 +79,12 @@ long compat_arm_syscall(struct pt_regs *regs)

		case __ARM_NR_compat_set_tls:
		current->thread.tp_value = regs->regs[0];

		/*
		* Protect against register corruption from context switch.
		* See comment in tls_thread_flush.
		*/
		barrier();
		asm ("msr tpidrro_el0, %0" : : "r" (regs->regs[0]));
		return 0;

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